Method of making integrated circuits with tub-ties

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438223, 438224, 438227, 438228, 257369, 257371, H01L 218238

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active

060543426

ABSTRACT:
An IC comprises a tub of a first conductivity type, at least one transistor embedded in the tub, and a first pair of isolating regions defining therebetween a tub-tie region coupled to the tub. The tub-tie region comprises a cap portion of the first conductivity type and an underlying buried pedestal portion of a second conductivity type. At least a top section of the pedestal portion is surrounded by the cap portion so that a conducting path is formed between the cap portion and the tub. In a CMOS IC tub-ties of this design are provided for both NMOS and PMOS transistors. In a preferred embodiment, the cap portion of each tub-tie comprises a relatively heavily doped central section and more lightly doped peripheral sections, both of the same conductivity type.
In accordance with another aspect of our invention, a reduced-mask-count CMOS IC process includes forming the isolating regions so that each has a protrusion which extends over the surface regions where the peripheral sections of the cap portion are to be formed. Then, a combination of ion implantation energies and concentrations, as well as suitable PR masking, in conjunction with the shape of the isolating regions, enables selective doping of the pedestal portion.

REFERENCES:
patent: 4905073 (1990-02-01), Chen et al.
patent: 5571745 (1996-11-01), Horiuchi
U. Schwalke et al., Exitgate. . . , 27th European Solid-State Research Conference, Stuttgart, Germany, Sep. 22-24, 1996, pp. 317-320.
U. Schwalke et al.,Advanced Gate-Stack. . . , 1997 Symposium on VLSI Technology, Jun. 10-12, 1997, Digest of Technical Papers, pp. 71-72.
C. P. Chang et al.,A Highly Manufacturable. . . , 1997 IEDM, Dec. 7-19, 1997, Technical Digest., pp. 661-665 (1997).

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