Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-03-11
2008-03-11
Ullah, Akm (Department: 4137)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S154000, C438S206000
Reexamination Certificate
active
07341905
ABSTRACT:
A process for making an integrated circuit is described wherein sequence of mask steps is applied to a substrate or epitaxial layer of p-type material. The sequence consists of sixteen specific mask steps that permit a variety of bipolar/CMOS/DMOS devices to be fabricated. The mask steps include (1) forming at least one N-well in the p-type material, (2) forming an active region, forming a p-type field region, (4) forming a gate oxide, (5) carrying out a p-type implantation, (6) forming polysilicon gate regions, (7) forming a p-base region, (8) forming a N-extended region, (9) forming a p-top region, 10) carrying out an N+ implant, (11) carrying out a P+ implant, (12) forming contacts, (13) depositing a metal layer, (14) forming vias, (15) depositing a metal layer therethrough, and (16) forming a passivation layer. Up to any three of mask steps (4), (7), (8), and (9) may be omitted depending on the type of integrated circuit.
REFERENCES:
patent: 4546370 (1985-10-01), Curran
patent: 5541125 (1996-07-01), Williams et al.
patent: 5556796 (1996-09-01), Garnett et al.
patent: 5856695 (1999-01-01), Ito et al.
patent: 5899714 (1999-05-01), Farrenkopf et al.
patent: 5917222 (1999-06-01), Smayling et al.
patent: 6022778 (2000-02-01), Contiero et al.
patent: 6130458 (2000-10-01), Takagi et al.
patent: 27 53 704 (1979-06-01), None
patent: 0 267 882 (1988-05-01), None
patent: 0 569 204 (1993-11-01), None
patent: 0 708 482 (1996-04-01), None
Ludikhuize A. W. “A Versatile 700-1200-V IC Process for Analog and Switching Applications”; IEEE Transactions on Electrontic Devices, Jul. 1, 1991; pp. 1582-1589; vol. 38, No. 7; IEEE Inc. ; New York, US.
Tsui P G Y et al. “A Versatile Half-Micron Complementary BICMOS Technology for Microprocessor-Based Smart Power Applications”; IEEE Transactions on Electron Devices; Mar. 1, 1995; p. 564-570; vol. 42, No. 3; IEEE Inc. ; New York, US.
Hamada K. et al. “A 60 V BICDMOS Device Technology for Automotive Applications”; Industry Applications Conference, 1995, Thirtieth IAS Annual Meeting, IAS '95; Oct. 8, 1995; p. 986-990; vol. 2; IEEE; New York, NY, US.
Fujishima N. et al. “High Packing Density Power Bi-CDMOS Technology and its Application for a Motor Driver LSI”; Power Semiconductor Devices and ICS, 1993; May 18, 1993; p. 298-303; IEEE; New York, NY, US.
Chan W. W. T. “A Novel Crosstalk Isolation Structure For Bulk CMOS Power IC'S”; IEEE Transactions on Electron Devices; Jul. 7, 1998; p. 1580-1586; vol. 45, No. 7; IEEE Inc. ; New York, US.
Martel Stephane
Michel Sebastien
Ouellet Luc
Riopel Yan
(Marks & Clerk)
DALSA Semiconductor Inc.
Ford Kenisha V
Mitchell Richard J.
Ullah Akm
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