Method of making buried contact in DRAM technology

Details Method of making buried contact in DRAM technology Method of making buried contact in DRAM technology

1996-06-24

1998-12-08

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438251, 438666, 438564, 148DIG20, H01L 218242

Patent

active

058468609

ABSTRACT:
A new method of forming an improved buried contact junction is described. Word lines are provided over the surface of a semiconductor substrate. A first insulating layer is deposited overlying the word lines. The first insulating layer is etched away where it is not covered by a buried contact mask to provide an opening to the semiconductor substrate. A layer of tetraethoxysilane (TEOS) silicon oxide is deposited over the first insulating layer and over the semiconductor substrate within the opening. The TEOS layer is anisotropically etched to leave spacers on the sidewalls of the word lines and of the first insulating layer. A first layer of polysilicon is deposited overlying the first insulating layer and within the opening. The first polysilicon layer is doped with dopant which is driven in to form a buried contact junction within the semiconductor substrate under the opening. The first polysilicon layer is patterned to form a polysilicon contact overlying the buried contact junction wherein the mask used for the patterning is misaligned and wherein a portion of a TEOS spacer overlying the buried contact junction is exposed and wherein a portion of the first polysilicon layer other than that of the contact remains as residue. The first polysilicon layer residue is etched away wherein the exposed TEOS spacer protects the buried contact junction within the semiconductor substrate from the etching completing the formation of a buried contact in the fabrication of an integrated circuit.

REFERENCES:
patent: 5198386 (1993-03-01), Gonzalez
patent: 5350712 (1994-09-01), Shibata
patent: 5491104 (1996-02-01), Lee et al.
patent: 5494848 (1996-02-01), Chin
patent: 5525552 (1996-06-01), Huang
S. Wolf, "Silicon Processing for the VLSI Era-vol. 2" Lattice Press, Sunset Beach, CA, pp. 160-162, 1990.

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