Method of making an electrically programmable memory cell

Details Method of making an electrically programmable memory cell Method of making an electrically programmable memory cell

1999-03-25

2001-10-02

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S267000, C438S593000, C438S596000, C438S696000

Reexamination Certificate

active

06297093

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of memory cells which can be made in MOS technology.
More specifically, the present invention relates to a memory cell including a control gate and a floating gate in which the floating gate is arranged laterally with respect to the control gate.
2. Discussion of the Related Art
U.S. Pat. No. 5,687,113, issued to Constantin Papadas and Bernard Guillaumot, assigned to the present assignee and incorporated herein by reference, describes such a cell in which the floating gate is arranged laterally with respect to the control gate.
FIG. 1
shows a memory cell of the type of that described in the above-mentioned patent. The cell is formed in a single-crystal silicon substrate
1
, more specifically in an active area of this substrate delimited by a thick oxide layer
2
. The upper surface of the semiconductor substrate is coated with a thin silicon oxide layer
3
on which is formed a polysilicon control gate
4
. The lateral walls of the polysilicon gate are insulated by a silicon oxide layer
5
and polysilicon spacers
7
and
8
are formed on either side of the gate. In the above-mentioned patent, conductive lateral spacers
7
and
8
are formed above respective source and drain extension areas
9
and
10
. For example, if the substrate is of type P, the source and drain extensions are of type N. Further, the cell includes more heavily doped N
+
-type source and drain areas
11
and
12
.
Of course, the cell illustrated in
FIG. 1
is not finished. To finish it, contacts need to be established with the source, drain, and control gate regions. The cell may include a single lateral spacer
8
above a drain extension.
The cell of this prior patent of the applicant provides satisfactory results. However, it is not compatible with all MOS integrated circuit manufacturing technologies and requires a double level of polysilicon layers, the first level corresponding to the control gate and the second level corresponding to a layer from which spacers
7
and
8
have been formed.
SUMMARY OF THE INVENTION
Thus, the present invention aims at providing an electrically programmable memory cell in which the floating gate is lateral with respect to the control gate and which is particularly simple to manufacture by methods compatible with the methods of CMOS structure manufacturing.
To achieve these and other objects, the present invention provides a method of manufacturing an electrically programmable memory cell with a floating gate lateral (i.e. disposed laterally) with respect to the control gate, including the steps of forming an insulated control gate on an active area; forming a thin insulating layer around the control gate; successively depositing a thin layer of a conductive material and a layer of an insulating material; anisotropically etching the insulating material to form spacers of this material; and removing the portions of the thin conductive layer which are not coated with the spacers.
According to an embodiment of the present invention, the conductive material is doped polysilicon.
According to an embodiment of the present invention, the conductive material has a thickness from 5 to 20 nm.
According to an embodiment of the present invention, the insulating material is silicon nitride.
According to an embodiment of the present invention, the method further includes the step of oxidizing the apparent portions of the conductive areas.
The present invention also relates to a memory cell with a control gate and a lateral floating gate, including on the lateral walls of the control gate insulating spacers under which is arranged a thin layer of a conductive material.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.


REFERENCES:
patent: 4620361 (1986-11-01), Matsukawa et al.
patent: 5429969 (1995-07-01), Chang
patent: 5687113 (1997-11-01), Papadas
patent: 5707897 (1998-01-01), Lee et al.
patent: 5736443 (1998-04-01), Park et al.
patent: 5759920 (1998-06-01), Burns, Jr. et al.
patent: 5760435 (1998-06-01), Pan
patent: 4-151852 (1992-05-01), None

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