Method of making a scalable two transistor memory device

Details Method of making a scalable two transistor memory device Method of making a scalable two transistor memory device

2001-06-21

2002-11-05

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000

Reexamination Certificate

active

06475857

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains in general to semiconductor devices, and more particularly to the manufacturing of a planar small dimensional memory cell array and its peripheral circuitry.
2. Description of Related Art
DRAM semiconductor devices have an advantage of a possible higher integration density as compared to other memory devices such as SRAM semiconductor devices, but DRAM semiconductor devices cannot maintain a decreasing stored charge, as required by scaling, due to leakage current from memory cells, internal noise, and soft errors caused by incident alpha particles. Therefore, the memory cells of such devices require constant refreshing in order to maintain data stored in the memory cells. Thus, power consumption is large even in stand-by mode.
Flash memory devices or EEPROM devices, on the other hand, have a merit in that there is no need to refresh the memory cells in order to maintain data stored in the memory cells. However, a primary drawback of flash memory devices is that it is difficult to improve its relative slow access time because it takes a relatively long time to program the memory cells. Moreover, a high voltage is necessary to program (write) or erase memory cells of flash memory devices. The high electric field applied during erase/write cycles degrades the SiO
2
tunneling barrier to the floating gate over a predetermined number (typically about 10
5
) of erase/write cycles and, as a result, limits the operational life of the memory device.
Thus, there is a need for a noble memory cell device that combines the advantages of DRAM and flash memory. In other words, there is a need for a semiconductor memory device having memory cells that allow scalable memory charge relative to cell density of the device with long-term retention, low voltage, high speed, and highly reliable operational characteristics. One such noble memory cell, which can be named as a Scalable Two-Transistor Memory cell, has been proposed by Nakazato et al. (refer to IEDM 97, pp. 179-182 and U.S. Pat. No. 5,952,692). Nakazato et al. referred to their device as a Planar Localized Electron Device Memory (PLEDM) cell. This memory cell has non-volatile, high-speed, very low-power dissipation, and high cell density characteristics. It also has an isolated memory node, which provides immunity against soft errors, a gain property, which provides a large S/N ratio. It is a quantum tunneling device working at room temperature with no hot carrier degradation effects, and can be fabricated by existing silicon processing technology.
FIG. 1
is a schematic diagram of a typical Scalable Two-Transistor Memory (here after referred to as STTM) cell. The STTM cell comprises a sensing transistor (
1
), which is also known as a read or an access transistor; and a programming transistor (
2
), which is also known as a write transistor. The sensing transistor is basically a conventional MOS transistor consisting of a floating gate (also acting as a storage node of the memory cell), a drain (acting as a sense line, S, corresponding to a bit line) and a source (acting as a ground line, G, at a ground or a certain potential). The programming transistor includes a multiple tunnel junction (MTJ) barrier structure, which is stacked on the storage node of the sensing transistor, with a control gate formed over the sidewalls of the barrier structure and the storage node, acting as a control gate line X (which is also known as the write line), and a source region which is electrically connected to the top region of the barrier structure acting as a data line Y. The storage node also acts as the drain region of the programming transistor. The programming transistor is basically a vertical channel transistor placed on top of a conventional floating gate MOS sensing transistor.
In the write mode, a data voltage is applied to the data line Y, and a write voltage (i.e., program voltage) is applied to the write (control gate) line X. Therefore, barrier height between the data line Y and the storage node is reduced, and tunneling current flows through the insulating layer. As a result, charges (electrons or holes) may be stored in the storage node. These stored charges change the threshold voltage of the sensing transistor. For example, in the event that the electrons are stored in the storage node and the sensing transistor is an NMOS transistor, the threshold voltage of the sensing transistor is increased towards the positive voltage. In a STTM cell, the write operation can be achieved with a low write voltage, as compared to the flash memory device. This is because in a STTM cell, the charge flow into the storage node is controlled by write (control gate) line X as well as the data line Y.
In order to read (sense) the data stored in a STTM cell, a read voltage is applied to the write (control gate) line X and an appropriate voltage is applied to the ground line G. Next, a sense amplifier (not shown) detects the current that flows through the sense line S. In this case, in the event that the threshold voltage of the sensing transistor is higher than the read voltage, the sense line current may not flow. If, however, the threshold voltage of the sensing transistor is lower than the read voltage, the sense line current may flow.
In the above STTM cell, the storage node is completely surrounded by insulating material (i.e., completely floated) unlike the storage node of a DRAM cell. Thus, in the event that the write voltage is much higher than the read voltage, there is no need to refresh the memory cells. Alternatively, the write (control gate) line can be separated into two write lines with the sensing transistor controlled by a first write line and the programming transistor controlled by a second write line. In this case, even though the write voltage approximates the read voltage, the programming transistor is not turned on during the read operation. Accordingly, it is not required to refresh the memory cell regardless of the difference between the write voltage and the read voltage.
As explained above, a unit STTM cell is operated by three control lines; the write (control gate) line, the bit line and the data line; whereas the unit DRAM cell is operated by only two control lines—the write line and the bit line. Thus, there continues to be a need for compact layout of the cell array region, data line extensions, and bit line extensions, in order to increase the integration density of STTM devices. Also, there continues to be a need for noble column addressing schemes to the bit lines and data lines in a limited cell pitch.
The present invention is directed to a processing sequence required for making a STTM cell array with a unit cell area as low as 4F
2
, where F is a minimum feature size, that corresponds to the width of the data line or write line and also the spacing between the data lines or the write lines. The processing sequence and conditions are designed to offer wide flexibility in terms of material choices and layer thickness at different regions of the STTM cell with surface planarity maintained at several stages of the manufacturing sequence. The processing sequence is designed for making both memory cell and peripheral devices simultaneously, to save the total processing time.
SUMMARY OF THE INVENTION
According to a feature of a preferred embodiment of the present invention, there is provided a self-aligned processing sequence for making a Scalable Two-Transistor Memory (STTM) cell array with a minimum unit cell area of 4F
2
, where F represents the minimum feature size and also the width (and also the spacing) of the data lines or the write (control gate) lines. An STTM cell consists of a sensing (bottom) transistor and a programming (top) transistor. The programming (top) transistor has a multiple tunnel junction (MTJ) barrier structure on the floating gate of a sensing MOS transistor. According to a preferred embodiment of the present invention, the method of the present invention provides processing sequence and processing conditions for f

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