Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1997-07-16
1999-03-09
Dinh, Son T.
Static information storage and retrieval
Read/write circuit
Bad bit
36523003, G11C 700
Patent
active
058810030
ABSTRACT:
A method of making a fault-tolerant memory device employing a variable domain redundancy replacement (VDRR) arrangement is described. The method includes the steps of: subdividing the memory into a plurality of primary memory arrays; defining a plurality of domains, at least one of the domains having at least a portion common to another domain to form an overlapped domain area, and wherein at least one of the domains overlaps portions of at least two of the primary arrays; allocating redundancy means to each of the domains to replace faults contained within each of the domains; and replacing at least one of the faults within one of the domains with the redundancy means coupled to the one domain, and at least one other fault of the one domain is replaced by the redundancy means coupled to another of the domains, if the at least one other fault is positioned within the overlapped domain area. Each redundancy unit supporting the primary memory arrays includes a plurality of redundant elements. Unlike the conventional fixed domain redundancy replacement scheme, redundancy units are assigned to at least two variable domains, wherein at least a portion of the domain is common to that of another domain. VDRR makes it possible to choose the most effective domain, and in particular, a smaller domain for repairing a random fault or a larger domain for repairing a clustered faults.
REFERENCES:
patent: 5295101 (1994-03-01), Stephen et al.
patent: 5430679 (1995-07-01), Hiltebeitel et al.
patent: 5459690 (1995-10-01), Rieger et al.
patent: 5461587 (1995-10-01), Oh
patent: 5475648 (1995-12-01), Fujiwara
patent: 5491664 (1996-02-01), Phelan
patent: 5633826 (1997-05-01), Tsukada
patent: 5751647 (1998-05-01), O'Tooloe
H. L. Kalter, et al, "A 50-ns 16-Mb DRAM with a 10-ns Data Rate and O-Chip ECC" IEEE Journal of Solid-State Circuits, V. 25, Oct. 1990, pp. 1118-1128.
T. Kirihata, et al, "A 14-ns 4-Mb CMOS DRAM with 300-mW Active Power" IEEE Journal of Solid-State Circuits, V. 27, Sep. 1992, pp. 1222-1228.
T. Sugibayashi, et al, "A 30ns 256Mb DTAM with Multi-Divided Array Structure" IEEE Journal of Solid-State Circuits, V. 28, Nov. 1993, pp. 1092-1098.
T. Kirihata, et al, "Fault-Tolerant Designs for 256 Mb DRAM" IEEE Journal of Solid-State Circuits, V. 31, Apr. 1996, pp. 558-566.
Daniel Garbiel
Dortu Jean-Marc
Kirihata Toshiaki
Pfefferl Karl-Peter
Dinh Son T.
International Business Machines - Corporation
Schnurmann H. Daniel
Siemens Aktiengesellschaft
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