Method of independent P and N gate length control of FET...

Details Method of independent P and N gate length control of FET... Method of independent P and N gate length control of FET...

2006-02-14

2006-02-14

Deo, Duy-Vu N. (Department: 1765)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S586000, C438S587000, C438S588000

Reexamination Certificate

active

06998332

ABSTRACT:
Disclosed is a method that forms a conductive layer on a substrate and patterns sacrificial structures above the conductive layer. Next, the invention forms sidewall spacers adjacent the sacrificial structures using a spacer material capable of undergoing dimensional change, after which the invention removes the sacrificial structures in processing that leaves the sidewall spacers in place. The invention then protects selected ones of the sidewall spacers using a sacrificial mask and leaves the other ones of the sidewall spacers unprotected. This allows the invention to selectively expose the unprotected sidewall spacers to processing that changes the size of the unprotected sidewall spacers. This causes the unprotected sidewall spacers have a different size than protected sidewall spacers. Then, the invention removes the sacrificial mask and patterns the conductive layer using the sidewall spacers as a gate conductor mask to create differently sized gate conductors on the substrate. Following this, the invention removes the sidewall spacers and forms the source, drain, and channel regions adjacent the gate conductors.

REFERENCES:
patent: 5759638 (1998-06-01), Imai et al.
patent: 6013570 (2000-01-01), Yu et al.
patent: 6100172 (2000-08-01), Furukawa et al.
patent: 6194268 (2001-02-01), Furukawa et al.
patent: 6207490 (2001-03-01), Lee
patent: 6350390 (2002-02-01), Liu et al.
patent: 6475891 (2002-11-01), Moon
patent: 6924191 (2005-08-01), Liu et al.
patent: 2001/0053570 (2001-12-01), Kido

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