Method of generating test clock signal and test clock signal...

Details Method of generating test clock signal and test clock signal... Method of generating test clock signal and test clock signal...

2007-09-27

2010-10-05

Ellis, Kevin L (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S724000

Reexamination Certificate

active

07810003

ABSTRACT:
A system and method of generating a test clock signal for scan testing of a main circuit in a semiconductor device includes receiving an external clock signal and a control signal and generating a gated clock signal by gating an internal clock signal based on the control signal. The internal clock signal has a frequency higher than a frequency of the external clock signal. One of the external clock signal and the gated clock signal is selectively output based on the control signal.

REFERENCES:
patent: 6711042 (2004-03-01), Ishikawa
patent: 2003/0009714 (2003-01-01), Evans
patent: 2006/0066368 (2006-03-01), Gabato et al.
patent: 2007/0174648 (2007-07-01), Panchal
patent: 11-329000 (1999-11-01), None
patent: 2001-159928 (2001-06-01), None
patent: 2005-140759 (2005-06-01), None
patent: 1020010074020 (2001-08-01), None
patent: 1020030005492 (2003-01-01), None

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