Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-19
2001-07-31
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S268000, C438S257000, C438S258000, C257S331000, C257S341000, C257S355000
Reexamination Certificate
active
06268242
ABSTRACT:
BACKGROUND OF THE INVENTION
A key objective in designing power MOSFETs is to reduce the on-resistance, i.e., the resistance of the MOSFET when it is turned on, to as low a value as possible. One way to achieve this objective is to reduce the channel resistance by increasing the cell density of the device. This increases the total cell perimeter and thereby provides a greater total gate width through which the current flows. Another way is to improve the transconductance of the active transistor portion of each cell by creating greater electrostatic coupling between the gate and the silicon which makes up the channel region of the device. This can be done be decreasing the thickness of the gate oxide layer (the layer, typically silicon dioxide, that separates the gate from the channel), which provides a lower threshold voltage and improved electrostatic coupling between the gate and the channel.
The gate oxide cannot be thinned without limit, however, because making the gate oxide thinner reduces the maximum gate voltage that can be applied to the device without rupturing the gate oxide and permanently destroying the MOSFET. It is difficult to design gate drive circuitry whose output is regulated within strict limits, and furthermore many circuits are subject to certain fault conditions (e.g., voltage spikes arising from transient conditions) that occasionally subject the gate to much higher than normal operating voltages. These conditions require the designer to thicken the gate oxide layer. In essence, the normal performance of the device is significantly compromised to protect against rare occurrences.
Thus there is a clear need for ways of safely reducing the thickness of the gate oxide layer and increasing the cell density of power MOSFET.
SUMMARY
According to the method of this invention, the gate oxide layer of a vertical MOSFET is protected by forming one or more voltage clamping diodes in a conductive path between the gate and the source of the MOSFET. The clamping diodes are formed by implanting N and P-type dopants into the same polysilicon layer that is used to form the gate. To minimize the number of additional masking steps required, one terminal of each diode is formed by implanting dopant into the polysilicon layer during the implantation of the body region of the MOSFET and the other terminal of each diode is formed by implanting dopant into the polysilicon layer during the implantation of the source region of the MOSFET. Thus, for an N-channel MOSFET the anode is formed with the body implant and the cathode is formed with the source implant. In some situations, additional dopant may be required to achieve the desired breakdown voltage of the diode. In other situations, particularly where a high breakdown voltage is required, the source or body implant may provide too much dopant and the polysilicon layer may have to be masked during the either or both of the source and body implants. In still other situations, only one of the diode terminals is formed by using the source or body implant, with the other terminal being doped a separate processing step.
The polysilicon layer in which the diodes are formed can be patterned, using standard photolithographic techniques, to create various arrangements of diodes. Metal layers are deposited and patterned to connect the diodes between the source and gate of the MOSFET to provide the voltage clamping function. In some embodiments, current-limiting resistors can be fabricated in the polysilicon layer to protect the diodes should the voltage need to be clamped.
As an additional aspect of the process, the lateral dimension between the gate sections in a vertical planar DMOSFET is reduced by self-aligning the gate with the contact to the source region. This avoids the need to be concerned about possible shorting between the gate and the contact which is inherent in a technology wherein the gate and the hole in which the contact is located are defined in successive masking steps as described above.
The first part of the process includes the formation of a the source and body regions in a vertical planar DMOSFET. Conventionally, this process begins with a semiconductor body which in many cases will comprise an epitaxial layer of a first conductivity type grown on a surface of a semiconductor substrate of the same conductivity type. A gate oxide layer is formed on a surface of the semiconductor body, and a conductive gate layer is formed on the gate oxide layer. A portion of the conductive gate layer is removed to define the gate, which is typically an interlinked lattice of sections connecting an array of MOSFET cells. A first dopant of a second conductivity type is implanted into the semiconductor body to form a body region, and the semiconductor body is heated to drive in the first dopant. A second dopant of the first conductivity type is implanted into the epitaxial layer to form a source region. In both of these implants the gate is normally used as a mask so that the source and body regions are self-aligned with the gate.
Importantly, an oxide layer is then formed overlaying the gate and a first portion of the source region. The oxide layer is anisotropically etched so to as expose a portion of the source region while leaving a spacer portion of the oxide layer on a sidewall of said gate, thereby forming a contact opening. The contact opening is thus self-aligned with the gate. The contact opening is then filed with a conductive material, typically a metal, so as to form an electrical contact to the source region.
There are numerous variations of this process. Frequently the gate will consist of doped polycrystalline silicone (polysilicon), and a layer of polysilicon oxide will be formed on top of the gate before the oxide layer is formed. The semiconductor body is often masked before the source implant to prevent the source dopant from reaching a portion of the semiconductor body, allowing a portion of the body region to remain at the surface of the semiconductor body. The anisotropic etching of the oxide layer exposes at least a portion of the body region so that the contact opening provides for a source/body contact.
What is described is thus a relatively simple means of reducing the lateral dimension between the gate sections and thereby increasing the density packing of the cells in a vertical planar DMOSFET. This holds the potential for significantly reducing the on-resistance of the DMOSFET without the added cost of using expensive steppers and other equipment.
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K. throngnumachai, “A Study on the Effects of the Gate Contact Geometry and Dimensions on ESD Failure Threshold Level of Power MOSFETs”, IEEE Trans. on Elec. Devices, vol. 41, n. 7, p. 1282.*
Kraison Throngnumchai, “A Study on the Effect of the Gate Contact Geometry and Dimensions on ESD Failure Threshold Level of Power MOSFET's”, IEEE Transactions on Eletron Devices, vol. 41, No. 7, Jul. 1994, pp. 1282-1287.
Grabowski Wayne B.
Williams Richard K.
Booth Richard
Simkovic Viktor
Skjerven Morrill & MacPherson LLP
Steuber David E.
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