Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-07-10
2002-11-19
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S254000, C438S396000, C438S397000, C438S692000
Reexamination Certificate
active
06482696
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 2000-39318, filed on Jul. 10, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a method of forming storage nodes in dynamic random access memory (DRAM) cell, and more particularly, to a method of forming a capacitor over bit line (COB) type cylindrical shaped storage nodes by using a silicon oxide layer of more than 8,000 Å as a molding layer.
DESCRIPTION OF THE RELATED ART
As the elements incorporated into a semiconductor device are integrated to a higher degree, the area occupied by capacitors decreases. Accordingly, various methods of increasing the capacitance of the capacitors have been prepared. Among these methods, forming capacitors over bit line to increase the surface area thereof is widely used.
At the start of the COB method, an overlying stacked capacitor structure is formed by depositing a high polysilicon layer and etching it to increase surface area thereof. However, recently the use of cylindrical shaped storage nodes has been adopted. The cylindrical shaped storage nodes are formed by depositing an oxide layer as a molding layer, forming holes in the oxide layer to have contact plugs to be exposed, and forming a conformal conductive layer in holes and on the oxide layer to be connected with the contact plugs.
However, as the aspect ratio of the cylindrical shaped storage node increases with increased integration of the semiconductor device, it becomes difficult to form an ideal cylindrical shaped storage node. One reason for this is that it is difficult to deeply and narrowly etch a molding oxide layer to form contact holes therein.
FIG. 1
is a cross-sectional view illustrating an etching problem of a molding layer
20
with holes
18
having a large aspect ratio manufactured in accordance with a conventional method. Due to slope etching, the deeper the molding layer
20
is etched, the narrower the etched holes
18
become. In some cases, contact plugs
25
disposed under the holes
18
are not exposed or are only partially exposed by etching. Then, it can be difficult for the contact plugs
25
to be electrically connected with a conductive layer
22
.
In addition to the interrupting of electrical connections between the contact plugs
25
and the conductive layer
22
, the narrowed width at lower portions of the etched holes
18
decreases surface areas of the storage nodes composed of the conductive layer
22
, thereby decreasing the capacitance thereof.
A method of forming storage node using the slope etching is disclosed in Japanese Patent Laid-open No.08-321542. According to the method, when forming an interlayer insulating layer, a lower layer is a material having relatively large etch speed such as a borophosphosilicate glass (BPSG), while an upper layer is a material having relatively low etch speed such as silicon nitride. Contact holes are formed in the interlayer insulating layer by the slope etching. Since during the etching, the silicon nitride layer generates polymers to form lots of slopes, contact holes having wide widths are formed in the upper silicon nitride layer, and contact holes having a width smaller than the wide width are formed in the lower layer, so that process margin can be increased.
Thus, an object of the conventional method does not prevent problems due to the slope etching, such as decrease of surface area and electrical disconnection, but decreases the width of the contact holes in the lower layer, to thereby increase the process margin by utilizing the slope etching. In addition, problems due to the slope etching still arise when using tetra ethylene ortho silicate layer (TEOS), cited as material having relatively high etch speed in the conventional method, as a molding oxide layer for forming storage nodes.
SUMMARY OF THE INVENTION
The present invention is therefore directed to a method of forming storage nodes in a dynamic random access memory device and resulting structure, which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
It is an object of the present invention to provide an improved method of forming COB type cylindrical shaped storage nodes which can form storage node holes having uniform widths in a tall molding layer, e.g., more than 8,000 Å.
It is another object of the present invention to provide an improved method of forming COB type cylindrical shaped storage nodes which can maintain capacitance of capacitors in DRAM cell at the designed value.
It is another object of the present invention to provide an improved method of forming COB type cylindrical shaped storage nodes which during forming storage node holes, can completely expose upper surfaces of contact plugs, thereby assuring storage nodes formed thereon to be electrically connected therewith.
It is another object of the present invention to provide an improved method of forming COB type cylindrical shaped storage nodes which use a multi-layered oxide layer structure formed to make relatively lower-positioned layer to have etching rate higher than that of relatively upper-positioned layer, as a molding layer, thereby reducing etching time and increasing etching efficiency.
These and other objects may be realized, according to the present invention, by a method of forming COB type cylindrical shaped storage nodes in DRAM cell, including forming a multi-layered structure composed of at least two silicon oxide layers as a thick molding layer, e.g., having a thickness of more than 8,000 Å, and the at least two silicon oxide layers being disposed to have etch speed of relatively lower-positioned silicon oxide layer to be relatively faster than that of relatively upper-positioned silicon oxide layer.
The relatively lower-positioned silicon oxide layer may be formed of BPSG or plasma enhanced oxide (PE-Ox), and the relatively upper-positioned silicon oxide layer may be formed of plasma enhanced tetra ethylene ortho silicate (PE-TEOS).
Also, the multi-layered structure may be formed to a thickness of more than 20,000 Å.
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Lebentritt Michael S.
Samsung Electronics Co,. Ltd.
Volentine & Francos, PLLC
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