Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-05-04
2002-07-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S653000
Reexamination Certificate
active
06426282
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to processing a substrate, e.g., a semiconductor wafer. In particular, the invention relates to a method and apparatus for depositing solder bumps on a semiconductor wafer.
2. Description of the Background Art
Microelectronic semiconductor substrates on which integrated circuits are formed require electrical contacts to provide the necessary interface between the integrated circuit and other electronic devices, such as printed circuit boards or user interface devices such as a monitor, keyboard, printer, mouse, or the like. With continuing advances in the semiconductor industry, circuits are often designed to use as little space as possible. Miniaturization of electrical circuits leads to many advantages including improved speed, noise reduction, and cost reduction. Despite increasing emphasis on miniaturization, reliable circuit interconnections must be formed on the semiconductor substrates.
Several methods may be used for forming the necessary electrical interconnections on semiconductor substrates. One method is to utilize lead frames that extend out of a plastic package in which a semiconductor device has been molded in order to connect with an external device. With increasing miniaturization, however, another approach known as “flip-chip” technology has widely come into practice. With “flip-chip” technology, electrical interconnects are provided by means of conductive metal bumps, known as solder bumps, constructed on bond pads that are formed on the top or active surface of the semiconductor substrate. The semiconductor substrate can then be “flipped” and mounted directly to a printed wiring board or other device, with the solder bumps forming the electronic interconnects. “Flip-chip” technology thus eliminates the need for semiconductor packaging, and also leads to many important advantages over other technologies used to form electrical interconnects including greater miniaturization, better interconnect reliability, higher circuit densities, and cost savings.
Vias are often utilized with integrated circuits (IC) to provide the interconnection necessary between the internal circuitry of the IC and the external interface, i.e., circuitry printed wiring boards and the like. Typically, a layered metallization using conventional metal deposition processes is utilized for the via bond pad, upon which a metal solder bump is constructed. A device is subsequently bonded to the substrate through the solder bump.
A semiconductor substrate typically undergoes a number of processing steps prior to the solder bump formation processing sequence. The process includes applying an adhesive and a diffusion barrier, such as titanium (Ti) and nickel vanadium (NiV) respectively over the via bond pad. The solder is then applied over the diffusion barrier and subjected to heating in order to create a reflow of the solder over the via bond pad.
The Ti/NiV layers (i.e., stack), usually deposits under a high tensile stress. Accordingly, stress control is extremely important during illustratively, a controlled collapse chip connection (“C
4
”) flip chip process. The C
4
flip chip process is an example of solder bump based flip chip technology known in the art. Tensile stress has been found to contribute to many failure mechanisms such as delamination, deformation, and fracture. Thus, it is desirable to keep the stress level at low tensile, or preferably in the compressive range to prevent the above mentioned failure mechanisms. Additionally, it has been found that stress is strongly dependent on deposition temperature and wafer bias. Therefore, there is a need to have the ability to integrate the NiV deposition process with sputtering hardware that is capable of providing active wafer temperature control, wafer bias, and full coverage.
SUMMARY OF THE INVENTION
A method for providing active wafer temperature control, wafer bias and full wafer coverage overcomes the disadvantages heretofore associated with the prior art. Specifically, the inventive method advantageously forms solder bumps on a semiconductor wafer utilizing a low temperature biasable electrostatic chuck. In particular, the method comprises the steps of providing at least one bond pad on the semiconductor wafer and depositing a barrier layer such as nickel vanadium over the at least one bond pad. Solder is then deposited over the barrier layer to form a solder bump on the bond pad.
Thus, by selecting an operating temperature and biasing power of the electrostatic chuck, the tensile stress or compressive strength of the barrier layer may be controlled. In this manner, the stress level of the titanium and nickel vanadium layers are maintained at low tensile, or preferably in the compressive range to prevent solder joint failures.
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Athreya Shankarram
Ngan Kenny King-Tai
Saigal Dinesh
Yang Lisa L.
Applied Materials Inc.
Dang Phuc T.
Moser Patterson & Sheridan LLP
Nelms David
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