Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-02
2001-10-30
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S239000, C438S248000, C438S386000, C438S391000, C365S149000, C365S182000
Reexamination Certificate
active
06309924
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to dynamic random access memory (DRAM) cells. More particularly, the present invention relates to a process for the formation of a thin insulating collar in the capacitive storage trench of DRAM cells.
2. Background and Related Art
Capacitive storage trenches are commonly employed in DRAM cells. A trench capacitor is a three-dimensional structure typically formed in a silicon substrate. A conventional trench capacitor is formed by etching a trench into the substrate. The trench is typically filled with n+ doped polysilicon which serves as one plate of the capacitor (referred to as the storage node). The second plate of the capacitor, referred to as a “buried plate,” is formed by, for example, outdiffusing n+ dopants from a dopant source into a region of the substrate surrounding the lower portion of the trench. A dielectric layer is provided to separate the two plates thereby forming the capacitor. To prevent or reduce parasitic leakage that occurs along the upper portion of the trench to an acceptable level, an oxide collar of sufficient thickness is provided therein. Typically, the oxide collar is sufficiently thick to reduce the parasitic leakage to an inappreciable amount. Typical of said prior art trench capacitor DRAM cells is that described in U.S. Pat. No. 5,981,332 to Mandelman, et al., entitled “Reduced Parasitic Leakage In Semiconductor Devices” and assigned to the assignees of the present invention.
It is known that continued demand to shrink devices has facilitated the design of DRAM cells with greater density and smaller feature size and cell area. For example, design rules have been scaled from 0.25 microns (&mgr;m) down to about 0.12 nm and below. At the smaller ground rules, the control of vertical parasitic MOSFET leakage from the buried-plate becomes more difficult due to the smaller trench dimensions. This is because a smaller trench opening necessitates a corresponding reduction in collar thickness to facilitate filling of the trench. However, to reduce the parasitic leakage to below an acceptable level, the thickness of the collar needs to be of some minimum dimension, depending on operating voltage conditions. Collar thickness hinders the filling of the smaller trench.
One of the difficulties in fabricating trench collars is that during high temperature process steps used in fabricating the cells, in general, there is a tendency for lateral growth or enlargement of the storage trench shape in the silicon substrate. This is particularly so during the process of thermal oxidation of material used to form the collar itself on the trench wall. Such oxidation steps can cause significant lateral growth of the storage trench due to simultaneous oxidation of the silicon substrate. This is particularly harmful in the fabrication of a hybrid DRAM cells where there is a vertically gated MOSFET within the same storage trench, with a bit line contact positioned above the adjacent vertical gate channel of the MOSFET. In such an arrangement, lateral growth of the trench reduces bit line contact area thereby limiting reduction in cell size or causing device failure.
Another difficulty with fabricating trench collars by means of oxidation of the silicon substrate is the ability to make the collars so they are uniform in thickness throughout the trench circumference without the bumps due to sporadic nucleation; and without thickness variations due to crystallographic effects on the local oxidation rate. Both effects make it difficult to effectively modulate the charge in the collar along the collar-silicon substrate interface. Inability to modulate the charge makes it difficult to control the vertical parasitic leakage and minimize the floating body effect.
SUMMARY OF THE INVENTION
In accordance with the teachings of the present invention, DRAM cells with capacitive storage trenches are fabricated having relatively thin insulating collar structures of uniform thickness throughout the circumference of the collar. Trenches are first formed in a silicon substrate. Then, an underlying nitride liner is formed on the silicon trench walls prior to depositing a layer of amorphous silicon thereon. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer. A layer of amorphous or polycrystalline silicon is then deposited, followed by the formation of a thin oxide on top of the amorphous/polycrystalline silicon, followed by the deposition of a thin silicon nitride layer on top of the thin oxide. A resist is then formed in the lower portion of the trench leaving the upper portion of the amorphous silicon layer exposed. The silicon nitride layer in the exposed upper portion of the trench is removed; followed by the removal of the resist in the lower portion of the trench. The upper portion of amorphous silicon (not covered by the silicon nitride layer) is then oxidized so as to consume all of the amorphous silicon and create a relatively thin, uniform collar along the entire trench circumference.
The nitride underlying the collar acts to enhance the thickness uniformity of the deposited amorphous silicon and thereby the uniformity of the resulting oxide collar. In addition, the nitride underlying the collar acts to limit lateral oxidation of the silicon trench walls during oxidation of the amorphous silicon layer with the oxidation of the amorphous silicon layer thereby being self-limiting. It should be noted that the nitride underlying the collar is also effective in cell operation to control the cell charge at the collar-substrate interface.
After formation of the collar, the silicon nitride, the oxide, the polycrystalline silicon (any amorphous silicon not oxidized would have crystallized into polycrystalline silicon), and the silicon nitride and oxide under the polycrystalline silicon layer in the lower portion of the trench is removed and a buried plate is formed in this lower portion. A node insulating layer is then formed on the buried plate and an n+ doped polysilicon fill is used to form the second plate or storage node. In vertical gate MOSFET applications, for example, trench top oxide is used to separate the storage node from the vertical MOSFET gate formed in the trench. In other MOSFET applications, the storage node may extend, for example, to the diffusion region of a lateral MOSFET at the surface of the substrate.
Accordingly, it is an object of the present invention to provide an improved trench capacitor memory cell.
It is another object of the present invention to provide an improved trench capacitor DRAM cell and method for making same.
It is yet another object of the present invention to provide a method of making a trench capacitor memory cell having a relatively thin insulating collar of uniform thickness overlying a thin layer of nitride in the upper portion of the trench.
It is a further object of the present invention to provide a method of fabricating a DRAM cell with trench capacitor that minimizes lateral growth or enlargement of the storage trench during fabrication heat treatment and thus maximizes cell electrical contact area at the surface.
It is yet a further object of the present invention to provide a method of making an insulating collar in the capacitive trench of DRAM cell so that oxidation of the layer of material used to form the collar is self-limiting.
These foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings, wherein like reference members represent like parts of the invention.
REFERENCES:
patent: 5406515 (1995-04-01), Rajeevakumar
patent: 5877061 (1999-03-01), Halle et al.
patent: 5909044 (1999-06-01), Chakravarti et al.
patent: 5937292 (1999-08-01), Hammerl et al.
patent: 5977579 (1999-11-01), Noble
patent: 5981332 (1999-11-01), Mandelman et al.
patent: 5985729 (1999-11-01), Wu
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patent
Divakaruni Ramachandra
Mandelman Jack Allan
McStay Irene Lennox
Nesbit Larry A.
Radens Carl John
International Business Machines - Corporation
Jordan John A.
Lytle Craig P.
Smith Matthew
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