Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-07-23
2001-07-24
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S592000, C438S596000
Reexamination Certificate
active
06265273
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits and to methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of forming rectangular shaped spacers in an integrated circuit.
BACKGROUND OF THE INVENTION
Transistors are generally formed on the top surface of a semiconductor substrate. Typically, the semiconductor substrate is divided into a number of active and isolation regions through an isolation process, such as field oxidation or shallow trench isolation. A thin oxide is grown on an upper surface of the semiconductor substrate in the active regions. The thin oxide serves as the gate oxide for subsequently formed transistors.
Polysilicon gate conductors are formed in the active regions above the thin oxide. The gate conductor and thin oxide form a gate structure which traverses each active region, effectively dividing the active region into two regions referred to as a source region and a drain region. After formation of the polysilicon gates, an implant is performed to introduce an impurity distribution into the source/drain regions. Generally, source/drain regions are heavily doped with n-type or p-type dopants.
Often a source extension and drain extension are disposed partially underneath the gate structure to enhance transistor performance. Source and drain extensions are extensions of the source and drain regions. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both n-channel and p-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-inducted barrier-lowering.
Spacers are structures which abut lateral sides of the gate structure and are provided over source and drain extensions. Preferably, spacers are silicon dioxide (SiO
2
) structures. Alternatively, other spacer materials, such as, silicon nitride (Si
3
N
4
), silicon oxynitride (SiON), or other insulators can be used. Conventional spacer formation tends to have a rounded shape in cross-section. The rounded shape of conventional spacers results in the redeposition of spacer materials during sputter processes. Spacer materials can be redeposited on nearby portions of the silicon substrate during sputter processes. For example, during sputtering of cobalt for cobalt film deposition, spacer materials are redeposited onto the nearby substrate. Redeposited spacer materials impede CoSi
2
formation. CoSi
2
provides increased performance due to reduced silicon resistance associated with contacts.
FIGS. 1-4
illustrate how conventional shaped spacers impede CoSi
2
formation in the integrated circuit fabrication process.
FIG. 1
illustrates a portion
10
of an integrated circuit including a substrate
12
, a gate structure
14
, and conventional shaped spacers
16
.
Substrate
12
is any of a variety of semiconductor materials. Gate structure
14
is aligned between active regions in substrate
12
. Gate structure
14
operates as an electrical switch for a stream of electrical charges, or “current,” to pass from one active region to another. Active regions are areas in portion
10
including impurities or dopants such as a p-type dopant (e.g., boron) or an n-type dopant (e.g., phosphorous). Conventional shaped shapers
16
are typically rounded and are made of insulating materials.
FIG. 2
illustrates a sputtering step in the integrated circuit fabrication process for cobalt film deposition. The rounded shape of spacers
16
results in the redeposition of spacer materials onto substrate
12
during the sputtering step. The redeposition of spacer materials over substrate
12
is not necessarily uniform over substrate
12
.
FIG. 3
illustrates a cobalt layer
18
, which is the result of the sputtering step. Layer
18
is deposited over substrate
12
, gate structure
14
, and conventional shaped spacers
16
.
FIG. 4
illustrates the resulting spotty formation of CoSi
2
due to redeposition of spacer materials over substrate
12
. Whereas the formation of CoSi
2
is satisfactory on gate structure
14
, formation of CoSi
2
is not uniform on substrate
12
due to the presence of redeposited spacer materials. Spotty or non-uniform CoSi
2
does not provide the advantageous effects CoSi
2
layers, such as, reducing series resistance associated with the contacts.
Thus, there is a need for a method of forming spacers with reduced surface area exposed to direct sputter such that spacer material is not redeposited during sputter processes. Further, there is a need for a method of forming rectangle shaped spacers. Even further, there is a need for uniform cobalt silicon formation in integrated circuit fabrication.
SUMMARY OF THE INVENTION
One embodiment of the invention relates to a method of forming spacers in an integrated circuit. The method includes providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure and etching the spacer material to form spacers. The spacers have minimal surface area exposed to direct sputter.
Another embodiment of the invention relates to a method of forming rectangle shaped spacers in an integrated circuit. The method includes forming a gate structure on a substrate, depositing a spacer material over the gate structure and the substrate, polishing the spacer material off of the top of the gate structure, and etching the spacer material to form spacers. The spacers have minimal surface area exposed to direct sputter.
Another embodiment of the invention relates to an integrated circuit. The integrated circuit includes a substrate, at least one gate structure on the substrate, and spacers. The spacers abut lateral sides of the at least one gate structure and have relatively vertical sidewalls.
REFERENCES:
patent: 5102815 (1992-04-01), Sanchez
patent: 5688704 (1997-11-01), Liu
patent: 6010954 (2000-01-01), Ho et al.
Avanzino Steven C.
Morales Guarionex
Park Stephen Keetai
Rangarajan Bharath
Shields Jeffrey A.
Advanced Micro Devices , Inc.
Foley & Lardner
Lindsay Jr. Walter L.
Niebling John F.
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