Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-06
2003-08-12
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06605513
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of forming nickel silicide using a one step rapid thermal anneal and backend processing process.
DESCRIPTION OF RELATED ART
Forming self-aligned suicides is well known in the semiconductor processing industry as a way of integrating low resistivity material on predefined regions of semiconductor structures that are being processed to form semiconductor devices. More specifically, self-aligned silicide processing is a method of reacting metal with silicon regions of a semiconductor structure to form silicide regions. Self-aligned silicides can be selectively formed on semiconductor structures without the necessity of patterning or etching the deposited silicide to define low resistively regions.
Titanium, cobalt, and nickel are among the metals that have been reacted with silicon materials to form self-aligned silicides on semiconductor structures. Titanium silicide can be formed on a semiconductor structure in a self-aligned manner.
FIG. 1
shows an exemplary silicon substrate
10
with a polycrystalline silicon region
16
formed on the silicon substrate
10
. Adjacent to the polycrystalline silicon region
16
are spacers
14
. The spacers
14
can be an oxide, nitride, or other ceramic material. The silicon substrate
10
has active regions
12
that can be characterized as being doped silicon and may function as the source and drain of a transistor. In
FIG. 2
, a layer of titanium metal or titanium alloy
18
is deposited over the semiconductor structure of FIG.
1
. The semiconductor structure of
FIG. 2
then undergoes a first rapid thermal anneal (RTA) at temperatures ranging from 550° C. to 750° C.
FIG. 3
shows the semiconductor structure of
FIG. 2
after this first rapid thermal anneal. Some of the titanium metal or titanium alloy layer
18
reacts with the polycrystalline region
16
to form high resistivity silicide (TiSi
2
) regions
22
. Additionally, some of the titanium layer
18
reacts with the silicon of the active region
12
to form high resistivity titanium silicide (TiSi
2
) region
20
. During the first rapid thermal anneal, none of the titanium layer
18
reacts with the spacer
14
. As silicide does not form on the spacers, the high resistivity titanium silicide regions
20
,
22
are formed in a self-aligned manner, as it is not necessary to pattern or etch silicide off the spacers to define the titanium silicide regions
20
,
22
on the polycrystalline region
16
and active region
12
. It is undesirable to form silicide on the spacers
14
as this leads to bridging between the gate and the source/drain
12
. Unreacted titanium in metal layer
19
of
FIG. 3
is stripped away using conventional stripping techniques.
FIG. 4
shows the semiconductor structure of
FIG. 3
after the unreacted metal layer
19
is stripped away. The high resistivity titanium silicide regions
20
,
22
remain integrated into the semiconductor structure after the wet strip of the unreacted metal
19
. The semiconductor structure of
FIG. 4
then undergoes a second rapid thermal anneal at temperatures ranging from 750° C. to 900° C.
FIG. 5
shows the semiconductor structure of
FIG. 4
after the second rapid thermal anneal where the high resistivity titanium silicide regions
20
,
22
are reacted to form low resistivity silicide (TiSi
2
) regions
24
,
26
. The low resistivity silicide titanium regions
24
are formed on the polycrystalline silicon region
16
and low resistivity titanium silicide regions
26
are formed on the active region
12
of the silicon substrate
10
.
There are several disadvantages of the above described two-step rapid thermal anneal process using titanium metal or titanium alloy to form low resistivity titanium silicide in a self-aligned manner. As semiconductor technology has advanced, it has become desirable for the dimensions of certain semiconductor structures to become smaller. For example, it is desirable for the polycrystalline region
16
and spacers
14
to be formed as small as possible on semiconductor substrate
10
to enhance performance of semiconductor devices using this type of structure. For example, transistors adopting this general semiconductor structure are designed and implemented with such small dimensions to enable the transistor to execute computer instructions at faster speeds. It is often necessary to form low resistivity titanium silicide regions on semiconductor structures to enable electrical interconnection of semiconductor components of a semiconductor device. Such exemplary regions are the active regions
12
and polycrystalline region
16
of FIG.
5
. The use of titanium in a two step rapid thermal anneal process to form titanium silicide in a self-aligned manner is not effective with semiconductor structures of smaller dimensions because titanium metal or titanium alloy layer does not fully react with the small surfaces of silicon materials such as the polycrystalline silicon region
16
and active regions
12
of
FIGS. 1-5
. The reasoning behind this shortcoming of titanium in a self-aligned silicide processes is that the reaction of titanium with silicon materials are dominated by nucleation of the silicide and therefore the silicide does not form in a consistent manner. As exemplified in
FIGS. 3-5
, the reaction of titanium metal or titanium alloy with the silicon materials forms titanium silicide regions that are scattered, inconsistent, and not adequate for the formation of silicide regions in some semiconductor devices, such as transistors. As not all of the titanium metal or titanium alloy reacts on the silicon material surfaces of small semiconductor structures, the reaction of titanium with the silicon based material does not adequately lower the resistivity of the silicon based components of the semiconductor structure. Hence, the use of titanium does not adequately serve the objectives of forming silicides in a self-aligned manner for relatively small semiconductor structures. This limitation of the use of titanium in self-aligned suicides is often referred to as line width dependence.
Another disadvantage of the use of titanium metal or titanium alloy to form titanium suicides in a semiconductor structure is that the temperatures at which the first and second rapid thermal anneal undergo are relatively high. These high temperatures limit the designs of the semiconductor structures utilizing self-aligned suicides. High temperatures can induce stress on the semiconductor structure and can destroy the functionality of the semiconductor device. Other disadvantages of a two-step rapid thermal anneal process to form titanium silicide are also known.
Cobalt can also be reacted with silicon materials, such as polycrystalline silicon or a silicon substrate, to form self-aligned cobalt silicide regions in a semiconductor structure.
FIG. 6
, for example, shows a semiconductor substrate
10
with active regions
12
and a polycrystalline region
16
formed on the silicon substrate
10
. Spacers
14
are formed on the silicon substrate
10
adjacent to the polycrystalline region
16
. A layer of cobalt metal or cobalt alloy
28
is formed on the semiconductor structure of
FIG. 6
, as shown in FIG.
7
. The semiconductor structure of
FIG. 7
undergoes a first rapid thermal anneal at temperatures ranging from 450° C. to 510° C.
FIG. 8
shows high resistivity cobalt silicide (CoSi) regions
30
,
32
formed on the polycrystalline region
16
and the active regions
12
as a product of the first rapid thermal anneal process. Any unreacted cobalt metal or cobalt alloy
29
is wet stripped away using conventional stripping techniques.
FIG. 9
shows the semiconductor structure of
FIG. 8
with high resistivity cobalt silicide
30
,
32
regions formed on the polycrystalline region
16
and the active region
12
of the substrate
10
after unreacted cobalt metal or cobalt alloy
29
is stripped away. No cobalt silicide is formed on the spacers
14
; this feature exemplifies the self-alignment characteristic of self-aligned silicides. Fur
Adem Ercan
Bertrand Jacques J.
Besser Paul R.
Buynoski Matthew S.
Foster John Clayton
Advanced Micro Devices , Inc.
Huang Quoc
Nelms David
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