Method of forming MOS transistor

Details Method of forming MOS transistor Method of forming MOS transistor

2005-11-08

2005-11-08

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S250000, C257S300000

Reexamination Certificate

active

06962840

ABSTRACT:
Methods of simultaneously forming MOS transistors and a capacitor on a substrate having gate insulation layers of varying thicknesses are disclosed. A method includes forming field regions in a substrate to define a first transistor region, a capacitor region, and a second transistor region, forming a first gate stack in the first transistor region and a lower electrode in the capacitor region, and forming an upper electrode on the lower electrode with a dielectric layer interposed therebetween and a second gate stack in the second transistor region.

REFERENCES:
patent: 5138412 (1992-08-01), Hieda et al.
patent: 5918119 (1999-06-01), Huang
patent: 6475862 (2002-11-01), Ando
patent: 2004/0004246 (2004-01-01), Anezaki
patent: 07-211861 (1995-08-01), None
patent: 2002-009168 (2002-01-01), None
patent: 1999-0042744 (1999-06-01), None
patent: 102000-0027814 (2000-05-01), None
Korean Patent Abstracts for Publication No. 1999-0042744.
Japan Patent Abstracts for Publication No. 2002-009168.
Japan Patent Abstracts for Publication No. 07-211861.
Korean Patent Abstracts for Publication No. 102000-0027814A.

Affiliated with

Also associated with

Rating

Method of forming MOS transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming MOS transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming MOS transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3494503