Method of forming interconnection lines for semiconductor...

Details Method of forming interconnection lines for semiconductor... Method of forming interconnection lines for semiconductor...

2007-03-20

2007-03-20

Hoang, Quoc (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S672000, C438S745000, C257S621000, C257SE21597

Reexamination Certificate

active

11049730

ABSTRACT:
The present invention discloses a method of fabricating interconnection lines for a semiconductor device. The method includes forming an interlayer insulating layer on a semiconductor substrate. A via hole is formed through the interlayer insulating layer. A via filling material is formed to fill the via hole. A photoresist pattern is formed on the via filling material. The via filling material and the interlayer insulating layer are anisotropically etched using the photoresist pattern as an etch mask to form a trench. A residual portion of the via filling material is removed using two wet etch processes. After removing the residual portion of the via filling material, a conductive layer pattern is formed in the via hole and the trench.

REFERENCES:
patent: 6465358 (2002-10-01), Nashner et al.
patent: 2005/0029229 (2005-02-01), Chae et al.
patent: 2006/0012014 (2006-01-01), Chen et al.

Affiliated with

Also associated with

Rating

Method of forming interconnection lines for semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming interconnection lines for semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming interconnection lines for semiconductor... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3755281