Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-01
2003-04-08
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S398000, C438S665000, C438S704000, C257S317000, C216S083000
Reexamination Certificate
active
06544842
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of cleaning and conditioning a semiconductor work object, such as a silicon wafer, so that subsequent process steps produce desired results. More particularly, the present invention provides a method of cleaning and etching a wafer so that deposition of amorphous silicon (“a-Si”) on the wafer produces good formations of Hemispherical Grained Silicon (“HSG”).
HSG formations enhance the storage capacitance in storage devices such as Dynamic Random Access Memory Arrays (“DRAMS”). Methods for forming HSG are described, for example, in U.S. Pat. Nos. 5,634,974 and 5,759,262, which are hereby incorporated by reference as if set forth in their entirety. More particularly, these patents describe a method of seeding and annealing a-Si on a polysilicon template on a wafer to form HSG. The polysilicon template may be formed in a layer of oxide material such as BPSG. When HSG is formed on the polysilicon template, it becomes the bottom plate of a capacitor device on the wafer.
During wafer transfer steps, a native oxide layer can form on the polysilicon template. As described in the aforementioned patents, the formation of a native oxide on a wafer's surface during wafer transfer steps causes significant problems in forming HSG structures on a wafer. This is because HSG formation is very sensitive to surface conditions. If the oxide layer is not removed or inadequately removed, it can impede the seeding step of the seeding/annealing process in HSG formation.
A persisting problem in HSG formation process is that existing process steps do not adequately etch the undesired oxide materials from the wafer. Poor, irregularly shaped HSG formations result if the HSG process is not conducted on clean, properly prepped wafers. There are further problems as well.
Existing techniques do not adequately passivate the wafer surface after etching. Passivation inhibits the reformation of native oxide. Another etch-related problem is that conventional etching techniques do not have acceptable selectivity ratios for the different materials present during HSG formation. This means either under-etching or over-etching of targeted materials on the wafer or over-etching of untargeted materials on the wafer. Conventional cleaning and etching techniques may also leave the wafer's surface in poor condition for HSG seeding and annealing steps. A brief overview of the cleaning and etching techniques used on wafers will help illustrate these problems in more detail.
Wafer cleaning steps are usually carried out before etching. Cleaning and etching techniques are well known in the art. The formulation and use of wafer cleaning solutions and various etchants for silicon dioxide, silicon, and other materials such, as silicon nitride are described, for example, in P. Van Zant,
Microchip Fabrication: A Practical Guide To Semiconductor Processing
(3
rd
ed. 1997) McGraw-Hill, New York, pp. 174-189 & pp. 259-283, which is hereby incorporated by reference. Sulfuric acid based solutions are commonly used to remove particulate and inorganic contaminants from the surface of a wafer. Generally, sulfuric acid based solutions are used at a temperature of about 90° C.-130° C. Oxidants may be added to the solution so that organic residues are removed from the wafer surface. Suitable oxidants include hydrogen peroxide, ammonium persulfate, nitric acid, and ozone.
Wet etching is commonly used to remove oxide and other materials from a wafer: wafers are immersed in an etchant tank for a predetermined time, then rinsed, and dried. Etchants that remove a top layer of material without substantially attacking an underlying layer are said to have high selectivity. The selectivity of an etchant is expressed as the ratio of the etch rate of one layer of material to the etch rate of another layer of material. Typically, selectivity ratios for silicon dioxide/silicon are about 20-40, depending on the etch method used.
Silicon oxide is the most commonly etched material on a wafer. Hydrogen fluoride (HF) is an attractive etchant because it dissolves silicon dioxide without removing substrate silicon. (As discussed below, this selectivity is contrary to good HSG formation.) However, at room temperature, at high concentrations, HF etches oxide too fast (about 300 Å/second). Therefore, HF is typically mixed with water and/or an ammonium fluoride (NH
4
F) buffering agent. When NH
4
F is in the solution, the solution is called a “buffered oxide etch” or “BOE” for short. It may be formulated at different strengths for different etch rates. BOEs may also include a wetting agent to reduce the surface tension of the etchant. One example BOE is an aqueous solution of HF and NH
4
F (1:8) at room temperature. The etch rate is about 700 Å/min. A more aggressive etchant for silicon dioxide is acetic acid and NH
4
F (2:1) at room temperature, which has an etch rate of about 1000 Å/min. Different etchants may be used to etch other material deposited on a wafer. For example, aqueous mixtures of nitric acid (HNO
3
) and HF have been used to etch polysilicon deposited on a wafer.
At least the following etchants have been used to remove the oxide layer from an HSG template prior to introducing the wafer into the seeding and annealing steps: (1) 100:1 wt. % HF solution; (2) HF vapor; and (3) unheated HF/TMAH solution. Unfortunately, these etchants suffer from the problems mentioned above: they may not etch polysilicon, or they under-etch or over-etch features on the wafer, or they do not condition a wafer well for seeding and annealing of HSG. For example, 100:1 HF and unheated HF/TMAH solutions are generally effective at etching a native oxide layer to expose the polysilicon template. However, these solutions do not etch the underlying polysilicon layer to any appreciable degree, at least not without over-etching oxide layers or rendering the polysilicon surface in an unsuitable condition for HSG formation. Still other etchants are problematic to use. For example, HF vapor etchants are not only highly aggressive (especially on BPSG) and difficult to control, but they also require more complicated application and containment equipment than required for etchant in solutions. HF vapor systems may also pose hazards to workers.
Another disadvantage of conventional etchants and methods is that they may not passivate the surface of the wafer adequately. Passivation inhibits the reformation of native oxide on the wafer that could occur during staging between process steps. This means shortened staging times between processing steps. Longer staging times are desirable to accommodate the lag between the cleaning and etching steps and the HSG formation steps.
For the foregoing reasons, there is a significant need for improved methods for cleaning and etching methods. The etchants used in such methods must etch selectivity ratios that are not too high or low and must leave the wafer in good condition for HSG formation. They should also passivate the wafer surface to inhibit reformation of oxide material during staging times.
SUMMARY OF THE INVENTION
The present invention overcomes the disadvantages of the prior art by doing one or more of the following:
Cleaning the surface of a wafer without disrupting the integrity of HSG template.
Etching native oxide from an HSG template without over-etching other structures on the wafer.
Conditioning the HSG template for HSG formation by removing a thin layer of the HSG template.
Passivating the surface of the wafer to inhibit reformation of native oxide and increase staging time for the wafer.
One embodiment of the present invention is directed to a method of preparing a surface of a semiconductor work object for formation of HSG structures, comprising: providing a work object having at least one HSG template; treating the work object with a cleaning agent to clean the surface of the wafer; treating the cleaned work object with a conditioning agent to condition the template for HSG formation; and directly transferring the conditioned work o
Chen Guoqing
Pan James
Fahmy Wael
Ganz Bradley M.
Ganz Law PC
Lee Hsien Ming
Micro)n Technology, Inc.
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