Method of forming flash memory

Details Method of forming flash memory Method of forming flash memory

2002-10-22

2004-05-04

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000, C438S259000, C438S257000, C257S315000, C257S317000

Reexamination Certificate

active

06730565

ABSTRACT:

RELATED APPLICATION
This application relies for priority upon Korean Patent Application No. 2001-80483, filed on Dec. 18, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a method of forming a flash memory and, more particularly, to a split gate type flash memory.
BACKGROUND OF THE INVENTION
Flash memories are non-volatile memory devices with a structure that is suitable for high integration density. Accordingly, recently, the flash memories are intensively studied and developed. In a conventional flash memory device, a memory cell gate pattern is made of a floating gate, a control gate, and a dielectric film interposed therebetween.
A novel dual gate type non-volatile memory is being developed, in which an erase operation is performed toward wordlines from a floating gate to generate a relatively lower erase voltage. Since the floating gate and a control gate of the novel memory are horizontally disposed, an opposite side thereof is relatively reduced and F-N tunneling is centralized to a tip of the floating gate (U. S. Pat. No. 5,029,130).
FIG.
1
and
FIG. 2
are cross-sectional views illustrating programming and erasing methods performed in a cell transistor of a non-volatile memory device having a floating gate and a control gate that are horizontally separated with a dielectric film interposed therebetween.
Referring now to
FIG. 1
, for programming, a high voltage Vdd is applied to a common source line
21
and a threshold voltage Vth is applied to a control gate line
120
. Further, a zero voltage (0V) is applied to a drain region
109
and a substrate
100
. Thus, electrons are moved from the drain region
109
to a source region
110
. By passing a tunneling gate insulating layer
15
, the electrons are accumulated into the floating gate
130
. That is, the programming is performed.
Referring now to
FIG. 2
, for erasing, a zero voltage (0V) is applied to the common source line
21
and a high voltage Vdd is applied to the control gate line
120
. Further, a zero voltage (0V) is applied to the drain region
109
and the substrate
100
. Thus, the electrons accumulated into the floating gate
130
are induced to the high voltage Vdd of the control gate line
120
. The induced electrons are moved to the control gate line through the tunneling gate insulating layer
15
. That is, the erasing is performed. Since an electric field is centralized to a tip
23
of the floating gate
130
, the electrons of the floating gate
130
are moved to the control gate line
109
through an insulating layer adjacent to the tip
23
.
FIG. 3
is a top plan view showing a layout in the case where a transistor device is realized in a cell area of a conventional split gate type flash memory. FIG.
4
through
FIG. 8
are cross-sectional views, taken along a line A—A of
FIG. 3
, showing the steps of forming the layout of FIG.
3
.
Referring now to
FIG. 3
, a device isolation layer
103
is formed to define an active region
101
that is formed along line A—A. A common source region or a common source line
21
is formed along a line C—C. A spacer oxide layer
115
, a control gate line or a wordline
120
, a spacer nitride layer
125
, and a substrate-exposing part are formed parallel to both sides of the common source region
21
or the common source line.
At an intersection of the active region
101
and the substrate-exposing part, a drain region
109
is formed at a substrate. In the drain region
109
, a bitline contact
107
will be formed in a subsequent process. As illustrated by bold lines, bitlines
105
are formed along the line A—A to cover the active region
101
. At an intersection of the active region
101
and the spacer oxide layer
115
, a floating gate
130
is formed under the spacer oxide layer
115
.
Referring now to FIG.
3
and
FIG. 4
, after stacking a tunneling gate insulating layer
15
and a floating gate layer on a substrate
100
, a trench type field oxide layer (trench type device isolation layer
103
of
FIG. 3
) is formed. The floating gate layer is partially removed to remain as a floating gate pattern
131
. Alternatively, a tunneling gate insulating layer and a floating gate layer are formed on a device-isolated substrate and by a patterning process, the floating gate pattern may remain only over the active region. A silicon nitride layer
115
is formed on an entire surface of the substrate
100
, and then a patterning process is carried out to form a silicon nitride pattern
135
exposing the common source region
110
and the spacer oxide layer
115
of FIG.
3
. The floating gate pattern
131
exposed between the silicon nitride patterns
135
is partially subjected to the thermal oxidation. An upper part of the floating gate pattern
135
is then oxidized to cause a bird's beak where an oxide layer
133
penetrates into a lower part of the silicon nitride pattern
135
at an interface between the patterns
131
and
135
.
Referring to now FIG.
3
and
FIG. 5
, a silicon oxide layer for a spacer is conformally formed on an entire surface of a substrate where the oxidized upper part of the floating gate pattern
131
is removed or unremoved. The silicon oxide layer is etched back to make the spacer oxide layer
115
remain on a sidewall of the silicon oxide layer pattern
135
. An unoxidized floating gate pattern
131
is exposed between the spacer oxide layers
115
. Using the spacer oxide layer
115
and the silicon nitride pattern
135
as an etch mask, the floating gate pattern
131
is continuously etched to remove the exposed floating gate pattern
131
. Concurrently, a tunneling gate insulating layer
15
is removed to expose the substrate
100
. Afterwards, impurities are implanted to form a source region
110
at an exposed substrate
100
. In one embodiment, this is performed with a dose of 10
15
ions/cm
2
. In a subsequent annealing process, the source region
110
will be extended to partially overlap with a floating gate region.
A section of the floating gate pattern
131
is exposed to a lower part of the spacer oxide layer
115
at a substrate
100
exposed to the source region
110
. After/before the implantation of the impurities, a thermal oxidation process is performed or a thin CVD oxide layer is formed to cover the section of the floating gate layer
131
.
Referring now to FIG.
3
and
FIG. 6
, the silicon oxide layer of the source region
110
is removed. A polysilicon layer is then stacked on an entire surface of the substrate to fill a space between the spacer oxide layers. By means of a CMP or an etch-back technique, the polysilicon layer is removed on an upper surface of the silicon nitride pattern
135
. As a result, the polysilicon layer remains only in the space between the spacer oxide layers
115
to form a common source line
21
.
Referring now to FIG.
3
and
FIG. 7
, the silicon nitride pattern
135
is removed by phosphoric acid or the like. By means of an anisotropic etch using the spacer oxide layer
115
as an etch mask, the floating gate pattern
131
is removed to form a floating gate
130
. Concurrently, an upper part of the common source line
21
may be partially removed. Further, the tunneling gate insulating layer
15
may be concurrently removed to expose the substrate
100
. A thin CVD oxide layer is conformally formed on an entire surface of the substrate
100
. Alternatively, a thermal oxidation process is carried out to form an oxide layer
116
covering a sidewall of the floating gate
130
exposed below the spacer oxide layer
115
and the exposed substrate
100
. During this procedure, the sidewall of the floating gate
130
may be partially oxidized to be laterally protruded.
Referring now to
FIG. 8
, a polysilicon layer
143
and a silicon nitride layer
145
are conformally formed on an entire surface of the substrate
100
in order to form a control gate or a wordline. The silicon nitride layer
145
may be substituted by a silicon oxynitride layer or the like.
Referring now to
FIG. 9
, an e

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