Method of forming flash EPROM by using iso+aniso silicon nitride

Details Method of forming flash EPROM by using iso+aniso silicon nitride Method of forming flash EPROM by using iso+aniso silicon nitride

1998-02-13

1999-12-14

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438257, 438303, 438305, H01L 21336

Patent

active

060016906

ABSTRACT:
A method is provided for forming nitride spacers for flash EEPROM devices. A silicon nitride layer is formed over the floating gate in a memory cell. Unlike in conventional methods where the nitride layer is usually subjected to anisotropic etching, it is disclosed in this invention that when partial isotropic/anisotropic etching of a particular recipe is performed, the resulting nitride spacers are better controlled dimensionally with the attendant advantage, therefore, of better definition of gate and channel lengths during subsequent implantations. In a second embodiment, the partial isotropic/anisotropic etching is followed by full anisotropic etching of another recipe with even better defined parameters for the flash EEPROMS.

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