Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-17
2003-07-15
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S003000, C438S240000, C438S396000, C438S640000, C438S673000, C438S701000
Reexamination Certificate
active
06593185
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a vertical three-dimensional MIM capacitor structure (metal-insulator-metal capacitor structure), and more particularly to a method for fabricating a vertical three-dimensional metal-insulator-metal capacitor (MIM Capacitor) structure that is compatible with the fabrication process of a copper dual damascene in logic integrated circuit and integration for copper dual damascene process.
2. Description of the Prior Art
Precision capacitors for complementary metal oxide semiconductor (CMOS) analog applications are generally metal-insulator metal (MIM) capacitor or polysilicon-insulator-polysilicon (PIP) capacitors.
However, PIP capacitors are becoming less popular because they present a number of problems when used with complementary metal oxide semiconductor (CMOS) technologies. More specifically, PIP capacitors are generally performed before the CMOS structures and the heat and oxidation cycles that occur during the CMOS production process degrade the PIP capacitors. Further, the sophistication of analog circuits is improving which requires that the variation in the capacitance be decreased and preferably maintained at a voltage of approximately 25 ppM. However, PIP capacitors suffer from carrier depletion that changes the capacitance as surface voltage across the PIP capacitor changes. Therefore, PIP capacitors do mot maintain the linearly required in today's sophisticated analog circuits. Further, PIP capacitors often trap charge within the insulator during their use.
Therefore, MIM capacitors, which are usually formed after the CMOS production process, are generally becoming more popular for analog circuits. However, MIM capacitors also present manufacturing problems. More specifically, conventional MIM capacitors with a SiO
2
insulator cannot be used over copper damascene metal wiring because copper diffuses through the capacitor structure and create leakage current. In other words, the copper is not a good electrode in the conventional capacitor structures. Therefore, conventional MIM capacitors are generally only used with aluminum wiring. This is a substantial disadvantage because copper dual damascene wiring is becoming popular in CMOS technologies because copper is less expensive and has better conductivity and electromigration resistance when compared to aluminum wiring. Therefore, there is a need for a process and structure that allow MIM capacitors to be used with copper dual damascene wiring.
In the present semiconductor mix mode integrated circuits process, the plate capacitor structure such as MIM capacitor as. showed in the FIG.
1
. The traditional plate MIM capacitor structure may includes a first metal line M
x
102
is embedded within the substrate
100
, wherein subscript x represents the xth metal layer. The plate MIM capacitor structure may also include a first plate (bottom plate)
104
on the substrate
100
, a first dielectric layer (bottom dielectric layer)
106
on the first plate
104
, a top plate (second plate)
108
on the first dielectric layer
106
, and a second plate dielectric (top plate dielectric)
110
on the second plate
108
. The second metal line M
x+1
112
contacts the exposed portion of the first metal line M
x
102
, wherein the subscript x+1 represents x+1th metal layer. In the traditional plate MIM capacitor structure, the plate MIM capacitor requires a large chip area to satisfy the designed capacitance. Further, the traditional plate MIM capacitor requires three extra photo-mask to define the first plate
104
, dielectric layer
106
, and second plate
108
, respectively and the process is difficult to be comparable with the copper dual damascene interconnect manufacturing flow.
SUMMARY OF THE INVENTION
In accordance with the present invention, a structure and a method is provided for forming a vertical three-dimensional metal-insulator-metal capacitor (MIM capacitor) on the substrate in logic integrated circuit and integration for copper dual damascene process, which is compatible with a copper dual damascene fabrication process, that substantially diminish the area of MIM capacitor at identical capacitance in logic integrated circuit.
It is one object of this invention is to provide a structure of a vertical three-dimensional MIM capacitor on the substrate that can diminish the space structure on the chip in logic integrated circuit.
It is another object of this invention is to provide a vertical three-dimensional MIM capacitor structure on the substrate to increase the capacitance density in logic integrated circuit.
It is a further object of this invention is to decrease the fabricating steps during the fabricating the vertical three-dimensional MIM capacitor structure.
It is still an object of this invention is to fabricate the vertical three-dimensional MIM capacitor structure with high capacitance density that the fabricating process is compatible with the copper dual damascene wiring process.
According to above-mention, an embedded capacitor applied to logic integrated circuit, such as a vertical three-dimensional MIM capacitor structure may be formed on a substrate, wherein the substrate having a remaining hard mask layer and a portion of the prior metal line therein. Herein, the portion of the prior metal line is used as a first metal electrode plate of the vertical three-dimensional MIM capacitor structure. The vertical three-dimensional MIM capacitor structure according to the present invention may include a second metal electrode plate that electrically coupled the first metal electrode plate by using a middle contact structure, wherein said middle contact structure on said first metal electrode plate being exposed on substrate. In the meanwhile, a copper dual damascene structure adjacent the vertical three-dimensional MIM capacitor structure on the substrate, and also electrically coupled the prior metal line being exposed on substrate. Due to the MIM capacitor structure is a vertical three-dimensional structure such that the requiring structure space of the capacitor structure on the chip can be diminished in the logic integrated circuit.
The process for forming a vertical three-dimensional MIM capacitor structure is compatible with a copper dual damascene structure fabrication process. The method for forming the vertical three-dimensional MIM capacitor is according to the present invention may include sequentially formed a first cap layer, a first dielectric layer, and a first hard mask layer on the substrate. Then, a via opening and a trench opening of the first layer of the copper dual damascene structure and the middle structure of the vertical three-dimensional MIM capacitor are formed simultaneously by using two photolithography processes, wherein the middle contact structure is used to electrically couple the first metal electrode plate. Next, a first copper layer is deposited to fill with the via opening and trench opening to form a first layer of the copper dual damascene structure, and the portion structure of the middle contact structure. Then, a second cap layer is formed on the above structure. Next, a third photoresist layer is covered on the copper dual damascene structure to form an opening of the middle contact structure. After the third photoresist layer is removed, a blanket insulator layer is deposited on the second cap layer that is not removed and on the sidewall of opening of the middle contact structure. Then, a second copper layer is deposited to fill with in the opening of the middle contact structure to form an inverse U-type contact, and the excess second copper layer is planarized by polishing process. Thereafter, a second dielectric layer and a second hard mask layer are sequentially formed on the structure of abovementioned after the second copper layer is planarized. Then, a second metal electrode plate and a second layer of the copper dual damascene structure (second metal electrode plate of the vertical three-dimensional MIM capacitor structure) are defined simu
Cheng Yi-Fang
Hsu Chia-Lin
Lin Yi-Hsiung
Tsai Teng-Chun
Jr. Carl Whitehead
Merchant & Gould P.C.
Nguyen Thanh
United Microelectronics Corp.
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