Method of forming dual damascene interconnection using low-k...

Details Method of forming dual damascene interconnection using low-k... Method of forming dual damascene interconnection using low-k...

2005-06-28

2005-06-28

Vinh, Lan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S703000

Reexamination Certificate

active

06911397

ABSTRACT:
A method of forming a dual damascene interconnection employs a low-k dielectric organic polymer as an insulating layer. With only one hard mask layer, ashing damage to the insulating layer is prevented using a hard mask layer and an etch-stop layer that are different in etch rate from that of a self-aligned spacer. Further, it is possible to form a via hole that is smaller than the resolution limit of the photolithographic process. As a result, the process is simplified and a photoresist tail phenomenon does not occur.

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