Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1996-11-26
2001-03-20
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S254000, C438S396000, C438S397000
Reexamination Certificate
active
06204113
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor integrated circuit fabrication method. More particularly, the present invention relates to a method of forming data storage capacitors with an increased capacitance in a dynamic random access memory (DRAM) of the DRAM cells, so as to maintain a high data retaining capability even if the DRAM chip is reduced in size to achieve higher integration.
2. Description of Related Art
A dynamic random access memory (DRAM) is a volatile semiconductor read/write memory that is widely used as the primary memory in most computers. The information age constantly requires DRAMs with higher integration so as to meet the demands of ever more sophisticated next generation applications. Therefore, it is a continuous research effort in the semiconductor industry to develop DRAMs with higher-packing densities of memory cells in a single DRAM chip.
A single DRAM chip includes a plurality of memory cells, each including at least a MOS transistor and a data storage capacitor (hereinafter referred to as a data storage capacitor) connected in series with the MOS transistor. The data storage capacitor is used to retain electric charges representative of the binary data “0” and “1”. These electric charges, however, will be gradually reduced in magnitude due to leakage. Therefore, periodic refreshing of these electric charges is required to enable the data storage capacitor to retain the binary data. It is usually desirable for the data storage capacitor to be formed with a sufficiently high capacitance so that electric charges can be reliably retained for an extended period of time. If the capacitance is too small, data stored in the DRAM cells could be easily lost within a short period of time.
Two approaches to increase the packing density of memory cells in a DRAM chip are presently used: (1) reduce the size of circuit elements of the DRAM chip, such as the length of interconnections and the width of gates of MOS transistors; and, (2) reduce the spacing between individual circuit elements. In future or next generation ULSI (Ultra Large Scale Integration) DRAMs, the data storage capacitors, or more specifically, the charge storage plates (electrodes) used to hold the electric charges will be proportionately reduced in size. It is known from fundamental circuit principles that the capacitance of a capacitor is proportional to the surface area of the charge storage plates. Therefore, a reduction in size of the data storage capacitors in DRAM cells will correspondingly reduce the capacitance of these data storage capacitors, causing these data storage capacitors to retain a reduced amount of electric charges. The binary data stored on the DRAM cells thus could be more easily and quickly lost due to leakage of the electric charges. To retain the data on the data storage capacitors, the DRAM cells need to be more frequently refreshed. However, during the refreshing period, read/write operations cannot be performed, thereby effectively reducing the performance of the DRAM cells. Therefore, in fabricating DRAM cells, it is always desirable to have high capacitance data storage capacitors.
FIG. 1
is a cross-section schematic view of a single DRAM cell having a data storage capacitor formed by a known conventional method. The DRAM cell is fabricated based on a silicon substrate
10
, on whose outer major surface a field oxide layer
12
and a gate oxide layer
14
are formed. A first conductive layer, such as a doped polysilicon layer, is formed on the outer surface of the substrate and is then selectively removed to form a gate
16
a
and a metal contact
16
b
. Spacers
18
a
and
18
b
are then formed respectively on the sidewalls of the gate
16
a
and of the metal contact
16
b
. A pair of N
+
source/drain regions
20
a
and
20
b
are formed in the silicon substrate
10
. An insulating layer
22
is formed over the outer surface of the substrate and then selectively removed to expose the source/drain region
20
b.
To form a data storage capacitor for the DRAM cell, a conductive layer
24
, a dielectric layer
26
, and another conductive layer
28
successively are formed on the outer surface of the substrate, with the layer
24
in contact with the region
20
b
. Conductive layers
24
and
28
can be, for example, doped polysilicon layers which serve as two opposing electrodes for the data storage capacitor. It is a drawback of the foregoing data storage capacitor that, when the feature size of the DRAM chip is reduced to increase the integration of memory cells on a chip, the surface areas of the conductive layers
24
and
28
will also proportionately be reduced, thus causing a decrease in capacitance of the storage capacitors. This will substantially decrease the charge retaining capability of the data storage capacitor.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method of forming data storage capacitors with increased capacitance in DRAM cells, so as to increase the data retaining capability of the DRAM cells.
In accordance with the foregoing and other objectives of the present invention, a new and improved method of forming a data storage capacitor in a DRAM cell is provided. In a method of the present invention, the first step is to prepare or provide a semiconductor substrate having at least a MOS transistor formed thereon and a first insulating layer formed over the MOS transistors and having an opening therethrough to expose one of the source/drain regions. The second step is to form a first conductive layer over the outer surface of the substrate, i.e., over the first insulating layer, and filling the opening. The next step is to form an insulating hump on the first conductive layer over the opening, which step preferably is carried out by forming a second insulating layer over the first conductive layer, and then selectively etching the second insulating layer to remove a selected part of the second insulating layer to form the insulating hump. The next step is to form a second conductive layer covering the first conductive layer and the insulating hump. Then a spacer of insulating material is formed on the sidewalls of a protruding portion of the second conductive layer that covers the insulating hump. The next step is to anisotropically etch the exposed portions of the first and second conductive layers using the spacer and the insulating hump as an etching mask to selectively remove part of the first and second conductive layers and to form at least a pair of trenches which extend into the first conductive layer to a given depth inside the region surrounded by the spacer and between the spacer and the insulating hump. Thereafter, the spacer and the insulating hump are removed from the substrate, and a dielectric layer covering the remaining parts of the first and second conductive layers is formed. Finally, a third conductive layer is formed over the dielectric layer.
In the semiconductor structure thus formed, the remaining part of the first and second conductive layers, the dielectric layer, and the third conductive layer in combination constitute the data storage capacitor of the DRAM cell. The double-trench structure in the data storage capacitor particularly increases the surface area of the bottom plate of the data storage capacitor, so that the capacitance of the data storage capacitor is also proportionally increased.
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Jr. Carl Whitehead
Kunitz Norman N.
Thomas Toniae M.
United Microelectronics Corp.
Venable
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