Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-03-05
2004-08-24
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S275000
Reexamination Certificate
active
06780708
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to the manufacture of semiconductor devices and, more specifically, relates to manufacturing semiconductor devices by forming core and periphery gates including two critical masking steps to form a hard mask in a core region that includes a critical dimension less than achievable at a resolution limit of lithography.
BACKGROUND ART
In the semiconductor industry, manufacturers scale down the device dimensions to increase the performance as well as reduce the cost of manufacture. The scaling down of devices has led to the development of several new processing techniques. In the manufacture of certain devices, wet etching has been replaced with dry etching (plasma etching, reactive ion etching and ion milling). Low-resistivity suicides and refractory metals are used as replacements for high-resistivity polysilicon interconnections. Multiple-resists have been developed to compensate for wafer surface variations that thwart accurate fine-line lithography.
However, improved lithography processing techniques continue to be the main factor in the ability to scale devices. Improvements have come in, for example, lithographic tools, such as 1:1 optical projection systems fitted with deep-ultraviolet source and optics. Further, new photoresist materials have been introduced. Further still, new processes have been developed, such as a multilayer resist utilizing a top resist sensitized to X-ray or electron-beam and a bottom straight optical resist layer(s).
DISCLOSURE OF INVENTION
Despite the enhancements to lithographic tools, materials and processes, there exists a strong need in the art for an invention which forms a line and space pattern including variable critical dimensions on a substrate sub-divided into regions. Further, there is a need for an invention that forms a line and space pattern in one region that includes a first feature comprising a first critical dimension different than a second critical dimension of a second feature in another region of the substrate. Further, there is a need to form one of the features to include a critical dimension less than achievable at a resolution limit of lithography. Additionally, there is a need for an invention that saves steps in a manufacturing process by reducing the number of steps used to form a mask used in the process. Additionally, there exists a need for an invention that forms gates and spaces comprising different critical dimensions in the regions of the substrate that reduces the processing steps required to form the gates and spaces.
According to one aspect of the invention, the invention is a method of forming a layer comprising a line and space pattern over a substrate including a first region and a second region, the method comprising the steps of:
depositing and patterning a hard mask layer over the layer to form a second line and space pattern therein, wherein the second line and space pattern includes at least one line and at least one space of a minimum dimension (D) dictated by a resolution limit of lithography;
depositing a conformal hard mask layer over the hard mask layer,
etching the conformal hard mask layer to form sidewall spacers on sidewalls of at least one line in the hard mask layer in the first region, whereby the minimum dimension (D) of the at least one space in the hard mask layer in the first region is reduced to a lateral dimension (A) less than achievable by the resolution limit of lithography; and
etching the layer to form the line and space pattern therein corresponding to a master line and space pattern in the hard mask layer in the first region and the second region, a space in the first region includes the lateral dimension (A) less than achievable by the resolution limit of lithography and a line in the second region includes a lateral dimension (B) achievable by lithography.
According to another aspect of the invention, the invention is a method of patterning a layer on a substrate including a first region and a second region, the method comprising the steps of:
providing the substrate including the layer to be patterned interposed between the substrate and a hard mask layer to be patterned;
coating the hard mask layer to be patterned with a first photosensitive layer;
patterning and etching the first photosensitive layer to form a first patterned image including lines and at least one space in the first region, the lines in the first photosensitive layer include substantially vertical walls and the at least one space includes a minimum dimension (D) dictated by a resolution limit of lithography;
transferring to the hard mask layer the first patterned image by anisotropically etching the hard mask layer in the first region to form lines and at least one space in the first region, the lines in the hard mask layer include substantially vertical walls and the at least one space includes the minimum dimension (D) dictated by the resolution limit of lithography;
depositing a conformal hard mask layer over the hard mask layer and exposed surfaces of the substrate;
coating the conformal hard mask layer with a second photosensitive layer;
patterning and etching the second photosensitive layer to form a second patterned image including at least one line and a space in the second region, the at least one line in the second photosensitive layer includes substantially vertical walls and a lateral dimension (B) determined by a device parameter;
transferring to the hard mask layer in the second region the second patterned image anisotropically etching the conformal hard mask layer and the hard mask layer to form at least one line and a space in the hard mask layer in the second region, the at least one line in the hard mask layer includes substantially vertical walls and a lateral dimension (B) dictated by the device parameter;
forming sidewall spacers on the vertical walls of the lines in the first region whereby the minimum dimension (D) of the at least one space in the first region is reduced; and
etching the layer to form a line and space pattern in the first region and the second region, an at least one space in the layer in the first region includes a lateral dimension (A) less than achievable by the resolution limit of lithography and a line in the second region is the at least one line that includes the lateral dimension (B) dictated by the device parameter.
According to another aspect of the invention, the invention is a semiconductor device, comprising:
a semiconductor substrate including a first region, a second region and an active region;
a dielectric layer formed over the semiconductor substrate; and
a conductive layer formed over the dielectric layer,
wherein the conductive layer includes:
a first pattern in the first region comprising lines and an opening, the opening includes a dimension (A) less than achievable by a resolution limit of lithography, and
a second pattern in the second region comprising at least one line including a lateral dimension (B) achievable by lithography.
REFERENCES:
patent: 4707218 (1987-11-01), Giammarco et al.
patent: 4792534 (1988-12-01), Tsuji et al.
patent: 5296410 (1994-03-01), Yang
patent: 5459345 (1995-10-01), Okudaira et al.
patent: 5747359 (1998-05-01), Yuan et al.
patent: 5766998 (1998-06-01), Tseng
patent: 5795830 (1998-08-01), Cronin et al.
patent: 5858834 (1999-01-01), Hirota et al.
patent: 5863707 (1999-01-01), Lin
patent: 6346724 (2002-02-01), Lee
patent: 6416933 (2002-07-01), Singh et al.
patent: 6482726 (2002-11-01), Aminpur et al.
patent: 6664180 (2003-12-01), Hui et al.
patent: 2001/0003034 (2001-06-01), Furukawa et al.
patent: 2001/0015454 (2001-08-01), Lee et al.
patent: 2002/0006585 (2002-01-01), Koh et al.
patent: 2002/0063277 (2002-05-01), Ramsbey et al.
patent: 0655773 (1995-05-01), None
patent: 04207076 (1992-07-01), None
Banerjee Basab
Behnke John R.
Foster Christopher M.
Kinoshita Hiroyuki
Sun Yu
Advanced Micro Devices , Inc.
Fourson George
Pham Thanh V
Renner , Otto, Boisselle & Sklar, LLP
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