Method of forming asymmetric MOS transistor with a channel...

Details Method of forming asymmetric MOS transistor with a channel... Method of forming asymmetric MOS transistor with a channel...

2008-05-27

2008-05-27

Weiss, Howard (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21429

Reexamination Certificate

active

07378320

ABSTRACT:
A MOS (metal oxide semiconductor) transistor with a trench-type gate is fabricated with a channel stopping region for forming an asymmetric channel region for reducing short channel effects. For example in fabricating an N-channel MOS transistor, a gate structure is formed within a trench that is within a P-well. A channel stopping region with a P-type dopant is formed to a first side of the trench to completely contain an N-type source junction therein. An N-type drain junction is formed within a LDD region to a second side of the trench, thus forming the asymmetric channel region.

REFERENCES:
patent: 5142640 (1992-08-01), Iwamatsu
patent: 5329148 (1994-07-01), Aoki
patent: 5371394 (1994-12-01), Ma et al.
patent: 5650340 (1997-07-01), Burr et al.
patent: 5693547 (1997-12-01), Gardner et al.

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