Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-12-11
2007-12-11
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S638000, C438S700000, C438S703000, C257SE21232, C257SE23145, C257SE21579
Reexamination Certificate
active
11099534
ABSTRACT:
A method of forming a via contact structure using a dual damascene process is disclosed. According to one embodiment a sacrificial layer is formed on an insulating interlayer during the formation of a preliminary via hole. The sacrificial layer has the same composition as a layer filling the preliminary via hole in a subsequent trench formation process. The sacrificial layer and the layer filling the preliminary via hole are simultaneously removed after the trench formation process is carried out. According to another embodiment, a thin capping oxide layer is formed on an insulating interlayer during the formation of a preliminary via hole. The thin capping oxide layer is removed together with a sacrificial layer after a trench formation process is carried out.
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patent: 6297149 (2001-10-01), Stamper
patent: 6461955 (2002-10-01), Tsu et al.
patent: 2006/0216926 (2006-09-01), Ye et al.
patent: 11-274299 (1999-10-01), None
patent: 1020030044338 (2003-06-01), None
Kim Jae-Hak
Lee Kyoung-Woo
Moon Young-Joon
Nam Seo-Woo
Shin Hong-Jae
Fourson George
Maldonado Julio J.
Samsung Electronics Co,. Ltd.
Volentine & Whitt PLLC
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