Method of forming a trench transistor having a superior gate...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S723000, C438S724000, C438S719000, C438S743000, C438S744000

Reexamination Certificate

active

06927134

ABSTRACT:
A trench transistor with lower leakage current and higher gate rupture voltage. The gate oxide layer of a trench transistor is grown at a temperature above about 1100° C. to reduce thinning of the oxide layer at the corners of the trench. In a further embodiment, a conformal layer of silicon nitride is deposited over the high-temperature oxide layer, and a second oxide layer is formed between the silicon nitride layer and the gate polysilicon. The first gate oxide layer, silicon nitride layer, and second oxide layer form a composite gate dielectric structure that substantially reduces leakage current in trench field effect transistors.

REFERENCES:
patent: 4326332 (1982-04-01), Kenney
patent: 4716126 (1987-12-01), Cogan
patent: 4746630 (1988-05-01), Hui et al.
patent: 4774556 (1988-09-01), Fujii et al.
patent: 4914058 (1990-04-01), Blanchard
patent: 4967245 (1990-10-01), Cogan et al.
patent: 4990463 (1991-02-01), Mori
patent: 5350937 (1994-09-01), Yamazaki et al.
patent: 5429977 (1995-07-01), Lu et al.
patent: 5498578 (1996-03-01), Steele et al.
patent: 5567634 (1996-10-01), Hébert et al.
patent: 5595927 (1997-01-01), Chen et al.
patent: 5665619 (1997-09-01), Kwan et al.
patent: 6046487 (2000-04-01), Benedict et al.
patent: 63288047 (1988-11-01), None
patent: 63288047 (1988-11-01), None
patent: 6422051 (1989-01-01), None
Kao et al., “Two-Dimensional Thermal Oxidation of Silicon-II Modeling Stress Effects in Wet Oxides”, IEEE, vol. ED-35, No. 1, Jan. 1988i.
Kao et al., “Two-Dimensional Thermal Oxidation of Silicon-I. Experiments,” IEEE Transactions on Electron Devices, vol. ED-34, No. 5, pp. 1008-1017, (May 1997).
Kao et al., “Two-Dimensional Thermal Oxidation of Silicon-II. Modeling Stress Effects in Wet Oxides,” IEEE Transactions on Electron Devices, vol. ED-35, No. 1, pp. 14, (Jan. 1988).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of forming a trench transistor having a superior gate... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming a trench transistor having a superior gate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a trench transistor having a superior gate... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3523347

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.