Method of forming a trench isolation layer and method of...

Details Method of forming a trench isolation layer and method of... Method of forming a trench isolation layer and method of...

2005-11-04

2009-10-13

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21680

Reexamination Certificate

active

07601588

ABSTRACT:
In a method of forming a device isolation layer for minimizing a parasitic capacitor and a non-volatile memory device using the same, a trench is formed on a substrate. A first insulation layer is formed on a top surface of the substrate and on inner surfaces of the trench, so that the trench is partially filled with the first insulation layer. A second insulation layer is formed on the first insulation layer to a thickness to fill up the trench, thereby forming a preliminary isolation layer. An etching rate of the second insulation layer is different from that of the first insulation layer. A recess is formed at a central portion of the preliminary isolation layer by partially removing the first and second insulation layers, thereby forming the device isolation layer including the recess. The recess in the device isolation layer reduces a parasitic capacitance in a non-volatile memory device.

REFERENCES:
patent: 6159801 (2000-12-01), Hsieh et al.
patent: 7151295 (2006-12-01), Yaegashi et al.
patent: 2002/0081817 (2002-06-01), Bhakta et al.
patent: 2003-031650 (2003-01-01), None
patent: 1020020088554 (2002-11-01), None

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