Method of forming a spacer

Details Method of forming a spacer Method of forming a spacer

2002-07-16

2003-04-22

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S595000

Reexamination Certificate

active

06551887

ABSTRACT:

RELATED APPLICATION
This application relies for priority upon Korean Patent Application No. 2001-53353, filed on Aug. 31, 2001, the contents of which are herein incorporated by this reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to methods of fabricating semiconductor devices, and more particularly to a method of forming a spacer.
BACKGROUND OF THE INVENTION
Generally, a semiconductor device may include a gate pattern formed on a semiconductor substrate and source/drain regions formed on the semiconductor substrate laterally from the gate pattern. As semiconductor devices become highly integrated, the size of the gate pattern is reduced and the space between the gate patterns becomes narrow. As the size of the gate pattern is reduced, the source region becomes closer to the drain region to produce an undesirable short-channel effect. In order to minimize the short-channel effect, a method of forming spacers at the sidewalls of the gate pattern has been conventionally employed. But, the spacers make the space between the gate patterns narrower and result in difficult processes for forming an interlayer dielectric layer filling the space between the gate patterns. In order to solve this problem, a technology of forming an L-shaped spacer has been provided.
FIGS. 1 through 3
are cross-sectional views illustrating a method of forming an L-shaped spacer according to a conventional technology, and problems caused thereby.
Referring to
FIG. 1
, an isolation layer pattern
20
is formed at a predetermined region of a semiconductor substrate
10
to define an active region. A gate oxide pattern
30
and a gate conductive pattern
40
are sequentially stacked over the entire surface of the semiconductor substrate. An ion-implantation process is performed by using the gate conductive pattern
40
as an ion-implantation mask to form a low concentration impurity region
45
at the semiconductor substrate
10
. A first insulation layer
50
, a second insulation layer
60
and a third insulation layer
70
are sequentially stacked over substantially the entire surface of the semiconductor substrate
10
including the low concentration impurity region
45
. The first insulation layer
50
is used as a buffer layer preventing a crystalline defect of a semiconductor substrate and an ion channeling phenomenon during an ion-implantation process for forming subsequent source/drain regions.
Conventionally, the first, second and third insulation layers
50
,
60
and
70
are formed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, respectively. The insulation layers
50
,
60
, and
70
form a spacer through a subsequent etching process, so that the thickness of the insulation layers determines the distance between the source region and the drain region. Thus, when the insulation layers are thick, an area of the active region for a contact becomes narrow, and if thin, the short-channel effect is induced.
Referring to
FIG. 2
, the third insulation layer
70
is anisotropically etched until the second insulation layer
60
is exposed to form a spacer
75
on the sidewalls of the gate conductive pattern
40
. The second insulation layer
60
acts as an etch stopping layer in the etching process. Then, the exposed second insulation layer
60
is etched by using the spacer
75
as an etch mask, until the first insulation layer
50
is exposed, and thus, a second insulation pattern
65
is formed.
The etching process for forming the second insulation pattern
65
is preferably an isotropic etching process. This is because it is difficult to determine an end of point in the anisotropical etching process, when a material layer to be etched is thin. The endpoint is a variable for determining the time when the etching process should be stopped. The endpoint is determined by using the fact that the compositions of exhaust gases are different in an etching process, when a material layer to be etched and another material layer thereunder are chemically different from one another. The second insulation layer
60
conventionally has a thickness of about 300 Å, but this thickness is too thin to determine the endpoint exactly. The thickness of the second insulation layer
60
is a variable affecting a subsequent process as explained in
FIG. 1
, thereby having a limit that cannot be freely increased. Thus, the etching process is preferably performed not by an anisotropical etching method but by an isotropic etching method.
When the second insulation layer
60
is etched by an isotropic etching method, as illustrated, the exposed surface of the second insulation pattern
65
is recessed. As a result, an undercut region
69
is formed at the bottom of the spacer
75
and the second insulation pattern
65
has a lower top surface than the spacer
75
.
When the second insulation layer
60
remains at the side of the spacer
75
, the remnant second insulation layer
60
acts as an etch stopping layer in a subsequent process of etching the first insulation layer
50
, and this results in a contact inferiority of a subsequent contact interconnection. Thus, the etching process of the second insulation layer
60
is preferably performed by an over-etch method until the first insulation layer
50
is properly exposed.
To summarize, the etching process of the second insulation layer
60
should be performed by an over-etch method using an isotropic etching method. But, this etching method etches a horizontally protruded part of the second insulation pattern
65
excessively, and thus, this results in a short-channel effect after source/drain regions are subsequently formed.
Referring to
FIG. 3
, an etching process is performed to remove the spacer
75
. In this process, the first insulation layer
50
formed of a silicon oxide layer like the spacer
75
is together etched to form a first insulation pattern
55
. This results in exposing the top surfaces of the isolation pattern
20
, the semiconductor substrate adjacent to the first insulation pattern
55
, and the gate conductive pattern
40
.
Impurities of high concentration are implanted by using the second insulation pattern
65
, the first insulation pattern
55
and the gate conductive pattern
40
as ion-implantation masks, to form source/drain regions
80
in the semiconductor substrate
10
. But, since the first insulation layer
50
on the source/drain regions
80
has been removed, an ion channeling phenomenon and a crystalline defect of a semiconductor substrate may occur during the implantation process. These problems happen because the first and third insulation layers
50
and
70
have no etch selectivity with respect to each other. Therefore, these problems occur even if the second insulation layer
60
is etched anisotropically.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of forming a spacer capable of preventing a short-channel effect by minimizing over-etching of a horizontally protruded part of a second insulation pattern.
It is another object of the present invention to provide a method of forming a spacer, where a buffer layer covers a semiconductor substrate in a process of forming source/drain regions in order to minimize ion channeling and crystalline defects.
The present invention is directed to a method of forming a spacer. The method uses material layers having different etch rates but having the same chemical composition. A gate pattern is formed on a semiconductor substrate. First, second, and third insulation layers are sequentially formed over substantially the entire surface of the resultant structure. The second and third insulation layers are formed under a first pressure and a second pressure higher than the first pressure, respectively. The third and second insulation layers are sequentially anisotropically etched to form a spacer and a second insulation pattern. The spacer is removed by using an etch recipe having an etch selectivity with respect to the second insulation pattern, thereby exposing the second insulation patte

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