Method of forming a silicon nitride layer in a semiconductor...

Details Method of forming a silicon nitride layer in a semiconductor... Method of forming a silicon nitride layer in a semiconductor...

2000-01-05

2002-04-16

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S792000

Reexamination Certificate

active

06372672

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor manufacturing, and, more particularly, to a method of forming a PE-CVD silicon nitride layer which exhibits good stress characteristics during a thermal process.
2. Description of the Related Art
A silicon nitride (SiN) film has been widely used as a passivation film or interlayer insulating film of integrated circuits.
FIGS. 1A
to
1
F schematically shows a method of forming a gate electrode with a low pressure (LP)-SiN capping layer, at selected stages according to the prior art. A gate oxide layer (not shown) is formed on a semiconductor substrate
2
. A gate electrode polysilicon
4
and a tungsten silicide
6
are deposited on the gate oxide layer as shown in
FIG. 1B. A
gate mask LP-SiN
8
, an oxide layer
10
and an anti-reflection layer (not shown) are formed on the gate electrode as shown in
FIGS. 1C and 1D
.
Referring to
FIG. 1E
, a photoresist pattern
12
is formed on the anti-reflection layer. Using the photoresist pattern
12
as an etching mask, underlying anti-reflection layer, oxide layer
10
and LP SiN layer
8
are etched. Then, the photoresist pattern
12
is removed. Using the etched LP SiN layer as an etching mask, the underlying tungsten silicide
6
and polysilicon
4
are etched to form a gate
14
as shown in FIG.
1
F. Subsequently, an annealing process is carried out so as to prevent hump generation on the sidewalls of the tungsten silicide during the gate spacer deposition process—particularly this process is high temperature oxide (HTO) deposition. Subsequently, a gate poly oxidation process is carried out. In turn, an insulating spacer made of HTO or LP-SiN is formed on a sidewall of the gate
14
.
As the degree of the integration density of the integrated circuit device increases, word lines and bit lines are made of titanium silicide or tungsten instead of tungsten silicide for improving device operation speed. This is because the titanium silicide and tungsten have lower resistivity than the tungsten silicide. However, there are some problems with the use of titanium silicide and tungsten in a gate electrode application. For example, gate mask LP-SiN and HTO are formed at high temperatures and such high deposition temperatures put a thermal budget on the titanium silicide and tungsten, thereby transforming the titanium silicide (e.g., titanium silicide layer partially agglomerates to form an iceberg-like region) and tungsten. As a result, when titanium silicide gate electrode layer is etched by using the overlying LP-SiN as a mask, the titanium silicide layer is selectively and partially etched.
As a result, after etching the gate electrode of polysilicon and titanium silicide, a gate electrode residue can remain on the semiconductor substrate where the gate electrode is not to be formed and a part of the semiconductor substrate can be etched to cause a pitting phenomenon.
In order to overcome the above-mentioned problems, the LP-SiN mask can be replaced by a PE-SiN layer, which can be formed at relatively lower temperatures, putting a smaller thermal budget on the underlying gate electrode. However, the PE-SiN has some problems with “a lifting phenomenon” from the underlying gate electrode. Such lifting phenomenon, for example, can be generated on the undercut region between the gate electrode and the mask PE-SiN following subsequent cleaning processes.
Another problem with conventional PE-SiN is a “popping phenomenon” of the PE-SiN (see reference number
20
of
FIG. 2
) caused by stress variation during hump treatment annealing process and the gate poly oxidation process. Reference number
20
represents the region where the PE-SiN layer is formed. As can be seen, popping of the PE-SiN exposes the underlying layer here and there. Reference number
21
indicates popping residues of the PE-SiN are scattered on the region adjacent to the PE-SiN formed region. Such popping phenomenon can block subsequent processes.
FIG. 3
schematically shows the relationship between stress and annealing temperature of the conventional PE-SiN. In
FIG. 3
, reference number
126
indicates a stress versus annealing temperature, and reference number
128
indicates a stress versus cooling following annealing. As can be seen, when annealing temperature is about 400° C., compressive stress begins to change into tensile stress, and the tensile stress significantly increases with increases in temperature. When temperature is about 850° C., the tensile stress becomes about 1.00E+10 dyne/cm
2
. As the temperature decreases after annealing, the tensile stress begins to change (i.e., increases) at about 650° C. and becomes about 1.30E+10 dyne/cm
2
at about 550° C. The stress varies significantly with respect to annealing temperature and furthermore the stress variation (&Dgr;S
1
) during and after annealing is very large. Such stress characteristics cause a popping phenomenon.
Accordingly, there is a need for a method of forming a silicon nitride that has a low stress variation during annealing and a low stress variation between during and after annealing.
SUMMARY OF THE INVENTION
The present invention was made in view of the above-mentioned problems and therefore is directed toward providing a method of forming a silicon nitride layer that can reduce stress variation during annealing process. The silicon nitride is formed in a controlled manner by a plasma enhanced chemical vapour deposition (PECVD) technique as to reduce hydrogen content, for example, to have hydrogen composition of about 0.35 or less. PECVD technique uses a silicon source gas selected from the group consisting of SiH
4
, Si
2
H
2
Cl
2
, and combinations thereof, uses a nitride source gas selected from the group consisting of NH
3
, N
2
, and combinations thereof. For example, PECVD technique uses a mixed gas containing SiH
4
, NH
3
and N
2
, and the ratio of SiH
4
:NH
3
is in the range of about 2:1 to 1:3 when SiH
4
is flowed at a rate of about 35 sccm to 60 sccm. The PECVD technique is carried out at a power of about 300 watt to 800 watt, at a pressure of about 5 torr to 7 torr, at a temperature of about 300° C. to 600° C.
In accordance with the present invention, there is provided a method of forming a silicon nitride layer(Si
x
N
y
H
z
) on a semiconductor topology in a semiconductor device, wherein a silicon nitride layer is formed by a plasma enhanced chemical vapor deposition(PE-CVD) technique to reduce a stress variation during an annealing process by adjusting hydrogen composition(z) of the silicon nitride layer to a predetermined value. The hydrogen composition preferably is at most 0.35.
In accordance with one aspect of the present invention, the semiconductor topology includes a semiconductor substrate and a material layer formed thereon, and wherein the silicon nitride layer and the underlying material layer are etched to define a gate electrode structure. The material layer is made of one selected from a group consisting of a refractory metal, a refractory metal silicide and refractor metal nitride. Refractory metal includes a tungsten, tantalum, molybdenum, titanium and cobalt, refractory metal silicide includes tungsten silicide, tantalum silicide, molybdenum silicide, titanium silicide and cobalt silicide, and the refractory metal nitride includes tungsten nitride, tantalum nitride and titanium nitride. An oxide layer may be further formed on the silicon nitride layer. Oxide layer may be made of one selected from a group consisting of high temperature oxide (HTO), PE-SiH
4
and PE-tetraethylorthosilicate (TEOS). An insulating spacer may be further formed on sidewalls of the etched material and silicon nitride layers. The insulating spacer is made of a PECVD silicon nitride layer having a hydrogen composition of at most 0.35.
In accordance with another aspect of the present invention, the semiconductor topology includes a semiconductor substrate and a pad oxide layer thereon, and wherein the silicon nitride layer, the pad oxide layer and the semiconductor substrat

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