Method of forming a semiconductor device using stress...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S216000, C438S305000, C438S199000, C438S508000

Reexamination Certificate

active

07858482

ABSTRACT:
A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film is removed, a second anneal is applied to the semiconductor device sufficiently long and at a sufficiently high temperature to activate dopants implanted for forming device source/drains. The result of this approach is that there is minimal gate dielectric growth in the channel along the border of the channel.

REFERENCES:
patent: 7144767 (2006-12-01), Chidambarrao et al.
patent: 7569499 (2009-08-01), Chidambaram
patent: 2005/0082634 (2005-04-01), Doris et al.
patent: 2008/0076215 (2008-03-01), Chuang et al.
patent: 2009/0032877 (2009-02-01), Visokay et al.
patent: 2009/0065880 (2009-03-01), Jain et al.
patent: 2009/0221117 (2009-09-01), Tan et al.
patent: 2009/0286365 (2009-11-01), Teo et al.
Eiho et al; “Management of Power and Performance with Stress memorization Technique for 45nm CMOS” 2007 Symposium on VLSI Technology Digest of Technical Papers, pp. 218-219.
PCT Search Report and Written Opinion, PCT/US2009/033187, Mailed Sep. 11, 2009.

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