Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-07-05
2010-06-08
Smith, Matthew (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S482000, C438S682000, C257SE21296, C257SE21297, C257SE21432
Reexamination Certificate
active
07732289
ABSTRACT:
A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain region, and siliciding at least a top portion of the additional layer. The additional layer compensates for at least a portion of the semiconductor material lost during manufacturing processes and increases the distance between the source/drain silicide and the substrate. As a result, the leakage current is reduced. A transistor formed using the preferred embodiment preferably includes a silicide over the gate electrode wherein the silicide extends beyond a sidewall boundary of the gate electrode.
REFERENCES:
patent: 5710450 (1998-01-01), Chau et al.
patent: 6015753 (2000-01-01), Lin et al.
patent: 6077750 (2000-06-01), Sohn et al.
patent: 6100145 (2000-08-01), Kepler et al.
patent: 6165900 (2000-12-01), Kim et al.
patent: 6365446 (2002-04-01), Chong et al.
patent: 6387803 (2002-05-01), Talwar et al.
patent: 6518155 (2003-02-01), Chau et al.
patent: 6630394 (2003-10-01), Lu et al.
patent: 6674135 (2004-01-01), Cheek et al.
patent: 7390707 (2008-06-01), Kawamura et al.
patent: 2002/0037610 (2002-03-01), Tseng
patent: 2002/0039830 (2002-04-01), Yeh et al.
patent: 2003/0219971 (2003-11-01), Cabral et al.
patent: 2004/0256671 (2004-12-01), Huang et al.
patent: 2005/0082522 (2005-04-01), Huang et al.
patent: 2005/0133834 (2005-06-01), Sorada et al.
patent: 2008/0070370 (2008-03-01), Wu et al.
patent: 56-50508 (1981-05-01), None
Öztürk, M.C. et al., “Ultra-Shallow Source/Drain Junctions for Nanoscale CMOS Using Selective Silicon-Germanium Technology,” Extended Abstracts of International Workshop on Junction Technology, 2001, pp. 77-82.
Öztürk, M.C., et al., “Low Resistivity Nickel Germanosilicide Contacts to Ultra-Shallow Si1−xGexSource/Drain Junctions for Nanoscale CMOS,” IEDM, 2003, pp. 497-500.
Öztürk; M.C., et al., “Advanced Si1−xGexSource/Drain and Contact Technologies for Sub-70 nm CMOS,” IEDM, 2002, pp. 375-378.
“ULSI Technology”, International Editions 1996, McGraw-Hill, p. 396.
Chang Chih-Chien
Chang Chih-Wei
Tsai Pang-Yen
Wu Chii-Ming
Jefferson Quovaunda
Slater & Matsil L.L.P.
Smith Matthew
Taiwan Semiconductor Manufacturing Company , Ltd.
LandOfFree
Method of forming a MOS device with an additional layer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a MOS device with an additional layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a MOS device with an additional layer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4197295