Method of forming a metal-oxide semiconductor transistor

Details Method of forming a metal-oxide semiconductor transistor Method of forming a metal-oxide semiconductor transistor

2002-09-10

2004-06-01

Cuneo, Kamand (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06743690

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices, more particularly, to a method of forming a metal-oxide semiconductor (MOS) transistor.
2. Description of the Related Art
In the manufacture of MOS transistors, offset spacers have been used to reduce the distance (known as “overlap”) between the gate and the shallow source/drain extension (SDE) extending under the gate. Also, SDE-to-gate overlap and vertical junction depth can be independently varied by varying the thickness of the offset spacer.
FIG. 1A
to
FIG. 1H
are cross-sections showing the manufacturing steps of a metal-oxide semiconductor (MOS) transistor having a offset spacer according to the prior art.
As shown in
FIG. 1A
, a semiconductor substrate
10
is provided having shallow trench isolation STI therein to define the active region. A gate oxide
12
is grown on the semiconductor substrate
10
in thermal ambient containing oxygen. Next, a doped polysilicon layer
14
is formed on the gate oxide
12
by low-pressure chemical vapor deposition (LPCVD).
Then, as shown in
FIG. 1B
, a photoresist pattern (for clarity, not shown) is formed on the polysilicon layer
14
at the predetermined position by photolithography. The polysilicon layer
14
and the gate oxide
12
are anisotropically etched to leave a polysilicon structure
14
a
, serving as the gate electrode, and a gate oxide
12
a
while the photoresist pattern is used as the etching mask. In this etching step, mechanical stresses are generated in the polysilicon structure
14
a
caused by ion bombardment.
The semiconductor substrate
10
is cleaned in an ultrasonic tank to remove undesirable particles and residues.
To eliminate mechanical stresses, the polysilicon structure
14
a
is annealed at an elevated temperature so that an oxide thin film
16
having a thickness of less than 50 angstroms is formed as shown in FIG.
1
C. In this step, the polysilicon structure can be rounded.
As shown in
FIG. 1D
, an insulating layer
18
, having a thickness of about 150 angstroms, such as silicon oxide or silicon nitride is deposited by low-pressure chemical vapor deposition at an elevated temperature.
As shown in
FIG. 1E
, the insulating layer
18
and the oxide thin film
16
are etched back to form an offset spacer OS consisting of an oxide spacer
16
a
and an insulator spacer
18
a
. Next, as shown in
FIG. 1F
, ions such as phosphorus or arsenic are implanted into the semiconductor substrate
10
to create lightly doped regions
22
,
24
.
Referring to
FIG. 1G
, a silicon nitride layer
26
, having a thickness of about 2500 angstroms, is deposited on the semiconductor substrate
10
and the gate electrode
14
a
. Next, as shown in
FIG. 1H
, the silicon nitride layer
26
is etched back to form a silicon nitride spacer
26
a
on the sidewall of the offset spacer OS.
Then, as shown in
FIG. 1H
, ions such as phosphorus or arsenic are implanted into the semiconductor substrate
10
to create heavily doped regions
28
,
30
serving as the source/drain region.
However, as the length of the polysilicon structure
14
a
for gate continues to shrink, the critical dimension (CD) of the polysilicon structure is not easily controlled by photolithography.
Furthermore, the polysilicon structure tends to peel from the semiconductor substrate
10
during ultrasonic cleaning.
Also, the offset spacer OS is manufactured by thermal oxidation of the oxide thin film
16
and deposition of the insulating layer
18
followed by etching of the oxide thin film
16
and the insulating layer
18
. Therefore, process complexity and manufacturing cost such as thermal budget is increased.
U.S. Pat. No. 5,981,325 to Hung discloses a method for manufacturing CMOS. A first offset spacer and a second offset spacer, double offset spacers, are sequentially formed on the sidewall of the gate electrode of CMOS by low-pressure chemical vapor deposition.
U.S. Pat. No. 6,187,644 to Lin et al. discloses a method of removing oxynitride by forming an offset spacer. A dielectric layer such as silicon oxide is deposited on the gate region. Then, the dielectric layer is subjected to etching back to form an offset spacer. Also, the dielectric layer has a thickness of about 100 to 600 angstroms.
However, the problems related to high manufacturing cost or peeling caused by deposition cannot be completely eliminated.
Therefore, a need has risen for providing an improved method of forming a metal-oxide semiconductor transistor.
SUMMARY OF THE INVENTION
In view of the above disadvantages, an object of the invention is to provide a method of forming a metal-oxide semiconductor (MOS) transistor in which the polysilicon structure is easily controlled by photolithography.
A further object of the invention is to provide a method of forming a metal-oxide semiconductor (MOS) transistor whose process complexity and manufacturing cost such as thermal budget can be reduced.
A further object of the invention is to provide a method of forming a method of forming a metal-oxide semiconductor transistor in which the adhesion between the polysilicon structure and the semiconductor substrate can be enhanced.
In accordance with one aspect of the invention, there is provided a method of forming a metal-oxide semiconductor (MOS) transistor. A semiconductor substrate is provided. A polysilicon layer is then deposited on the semiconductor substrate. The polysilicon layer is selectively etched to form a gate electrode. A silicon oxide layer is grown on the top and the sidewall. Ions (or dopants) are doped into the semiconductor substrate to form a lightly doped region. Then, a nitride spacer is formed on the sidewall of the silicon oxide layer. Finally, ions are doped into the semiconductor substrate to form a heavily doped region to serve as a source/drain of the MOS transistor.
In accordance with another aspect of the invention, the oxide layer is preferably etched back to form an oxide spacer serving as the offset spacer.
In accordance with a further aspect of the invention, the silicon oxide layer preferably has a thickness of about 60 to 180 angstroms. More preferably, the silicon oxide layer has a thickness of about 60 to 250 angstroms. Also, the oxide layer is preferably grown at a temperature of about 700° C. to 1200° C., more preferably, it is grown at a temperature of about 850° C. to 900° C. in an ambient containing oxygen for 3 to 4 hours.
In accordance with yet another aspect of the invention, the semiconductor substrate is cleaned in an ultrasonic tank after the polysilicon layer is etched to form a gate electrode.
Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.


REFERENCES:
patent: 5747373 (1998-05-01), Yu
patent: 5981325 (1999-11-01), Hung
patent: 6187644 (2001-02-01), Lin et al.
patent: 6498067 (2002-12-01), Perng et al.

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