Method of forming a metal gate in a semiconductor device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S305000, C438S595000, C257SE21621

Reexamination Certificate

active

07361565

ABSTRACT:
In a method of forming a metal gate in a semiconductor device, a gate insulation pattern and a dummy gate pattern are formed on a substrate. An insulation interlayer is formed on the dummy gate pattern to cover the dummy gate pattern. The insulation interlayer is polished such that a top surface of the dummy gate pattern is exposed, and the dummy gate pattern is selectively removed to form a trench on the substrate. A gate spacer is formed on an inner sidewall of the trench for determining a gate length of the metal gate. A metal is deposited to a sufficient thickness to fill the trench to form a metal layer. The metal layer is polished to remain in the trench. Accordingly, the gate length of the metal gate may be reduced no more than the resolution limit of the photolithography exposing system.

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patent: 10-313546 (2001-10-01), None

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