Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-04-10
2007-04-10
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S954000, C257S368000
Reexamination Certificate
active
11165330
ABSTRACT:
A method of forming a memory device includes forming a memory stack on a substrate. The memory stack includes an alumina layer acting as an intergate dielectric layer. A transistor is formed on the substrate in an area separate from the memory stack. The transistor is formed to include thin gate oxide via a dry oxidation technique and a gate layer on the thin gate oxide. The thin gate oxide is formed without subjecting the thin gate oxide to thermal annealing with N2O.
REFERENCES:
patent: 6706595 (2004-03-01), Yang et al.
patent: 6780708 (2004-08-01), Kinoshita et al.
patent: 6787840 (2004-09-01), Pham et al.
patent: 6808996 (2004-10-01), Pham et al.
patent: 6815292 (2004-11-01), Fang et al.
patent: 6835662 (2004-12-01), Erhardt et al.
Orimoto Takashi Whitney
Sachar Harpreet K.
Advanced Micro Devices , Inc.
Dang Phuc T.
Harrity & Snyder LLP
Spansion LLC
LandOfFree
Method of forming a memory device having improved erase speed does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a memory device having improved erase speed, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a memory device having improved erase speed will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3727984