Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-05-17
2000-11-28
Smith, Matthew
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438157, 438268, 438269, H01L 21336, H01L 2184
Patent
active
061534684
ABSTRACT:
A programmable memory address decode array with vertical transistors having single or split control lines is used to select only functional lines in a memory array. The transistor is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source regions and drain regions. If a particular floating gate is charged with stored electrons, then the transistor will not turn on and will act as the absence of a transistor at this location in a logic array within the decoder. The decoder is programmed at memory test to select an output line responsive to the bits received via the address input lines. A logic array includes densely packed logic cells, each logic cell having a semiconductor pillar providing shared source and drain regions for two vertical floating gate transistors that have individual floating gates and control lines distributed on opposing sides of the pillar. The control lines are formed together with interconnecting address input lines. The source regions share a common ground while the drain regions are connected to the output lines. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to represent a logic function, an area of only 2F.sup.2 is needed per bit of logic, where F is the minimum lithographic feature size.
REFERENCES:
patent: 4604162 (1986-08-01), Sobczak
patent: 4663831 (1987-05-01), Birrittella et al.
patent: 4716314 (1987-12-01), Mulder et al.
patent: 4845537 (1989-07-01), Nishimura et al.
patent: 4920065 (1990-04-01), Chin et al.
patent: 4949138 (1990-08-01), Nishimura
patent: 4958318 (1990-09-01), Harari
patent: 4965651 (1990-10-01), Wagner
patent: 5001526 (1991-03-01), Gotou
patent: 5006909 (1991-04-01), Kosa
patent: 5010386 (1991-04-01), Groover, III
patent: 5083047 (1992-01-01), Horie et al.
patent: 5087581 (1992-02-01), Rodder
patent: 5102817 (1992-04-01), Chatterjee et al.
patent: 5177576 (1993-01-01), Kimura et al.
patent: 5208657 (1993-05-01), Chatterjee et al.
patent: 5221867 (1993-06-01), Mitra et al.
patent: 5376575 (1994-12-01), Kim et al.
patent: 5414287 (1995-05-01), Hong
patent: 5416350 (1995-05-01), Watanabe
patent: 5432739 (1995-07-01), Pein
patent: 5460988 (1995-10-01), Hong
patent: 5466625 (1995-11-01), Hsieh et al.
patent: 5497017 (1996-03-01), Gonzales
patent: 5504357 (1996-04-01), Kim et al.
patent: 5519236 (1996-05-01), Ozaki
patent: 5528062 (1996-06-01), Hsieh et al.
patent: 5563083 (1996-10-01), Pein
patent: 5574299 (1996-11-01), Kim
patent: 5637898 (1997-06-01), Baliga
patent: 5674769 (1997-10-01), Alsmeier et al.
patent: 5705415 (1998-01-01), Orlowski et al.
patent: 5753947 (1998-05-01), Gonzalez
patent: 5818084 (1998-10-01), Williams et al.
patent: 5827765 (1998-10-01), Stengl et al.
patent: 5907170 (1999-05-01), Forbes et al.
patent: 5909618 (1999-06-01), Forbes et al.
patent: 5914511 (1999-06-01), Noble et al.
patent: 5920088 (1999-07-01), Augusto
patent: 5936274 (1999-08-01), Forbes et al.
patent: 5963469 (1999-10-01), Forbes
patent: 5973352 (1999-10-01), Noble
patent: 5973356 (1999-10-01), Noble et al.
patent: 5991225 (1999-11-01), Forbes et al.
patent: 6025225 (2000-02-01), Forbes et al.
patent: 6043527 (2000-03-01), Forbes
patent: 6066869 (2000-05-01), Noble et al.
patent: 6081449 (2000-06-01), Sekariapuram et al.
Asai, S., et al., "Technology Challenges for Integration Near and Below 0.1 micrometer", Proceedings of the IEEE, 85, Special Issue on Nanometer-Scale Science & Technology, 505-520, (Apr. 1997).
Bomchil, G., et al., "Porous Silicon: The Material and its Applications in Silicon-On-Insulator Technologies", Applied Surface Science, 41/42, 604-613, (1989).
Hisamoto, D., et al., "A New Stacked Cell Structure for Giga-Bit DRAMs using Vertical Ultra-Thin SOI (DELTA) MOSFETs", 1991 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C., 959-961, (Dec. 8-11, 1991).
Kang, H.K., et al., "Highly Manufacturable Process Technology for Reliable 256 Mbit and 1Gbit DRAMs", IEEE International Electron Devices Meeting, Technical Digest, San Francisco, CA, 635-638, (Dec. 11-14, 1994).
Maeda, S., et al., "A Vertical Phi-Shape Transistor (VPhiT) Cell for 1 Gbit DRAM and Beyond", 1994 Symposium of VLSI Technology, Digest of Technical Papers, Honolulu, HI, 133-134, (Jun. 7-9, 1994).
Maeda, S., et al., "Impact of a Vertical Phi-Shape Transistor (VPhiT) Cell for 1 Gbit DRAM and Beyond", IEEE Transactions on Electron Devices, 42, 2117-2123, (Dec. 1995).
Pein, H.B., et al., "Performance of the 3-D Sidewall Flash EPROM Cell", IEEE International Electron Devices Meeting, Technical Digest, 11-14, (1993).
Forbes Leonard
Noble Wendell P.
Malsawma Lex H.
Micron Technololgy, Inc.
Smith Matthew
LandOfFree
Method of forming a logic array for a decoder does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a logic array for a decoder, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a logic array for a decoder will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1724721