Method of forming a HVNMOS with an N+ buried layer...

Details Method of forming a HVNMOS with an N+ buried layer... Method of forming a HVNMOS with an N+ buried layer...

1999-05-25

2001-07-24

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

With means to increase breakdown voltage threshold

C257S370000, C257S034000

Reexamination Certificate

active

06265752

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and more specifically, to a high voltage NMOS with an n+ buried layer combined with N well.
BACKGROUND
For ultra large scale integrated (ULSI) circuits application, one of the features is to shrink the dimensions of devices down to sub-micron or deep sub-micron range. In NMOS, a channel region in the semiconductor under the gate is doped with ions that are opposite to that of the source and drain. The operation of the MOS includes the application of applying a voltage to the gate. By varying the transverse electrical field, it is possible to control the current flow by modulating the longitudinal conductance of the channel. If the drain bias is applied such that source-body and drain-body junctions remain reverse-bias. A positive bias is applied to the gate of the NMOS, electrons will be attracted to the channel region, once enough electrons are drawn into the channel region by the positive gate voltage, the channel connects the source and the drain.
One type of the NMOS is called a high voltage NMOS (HVNMOS), which can be operated under applying a high operation voltage.
FIG. 1
shows a prior art high voltage NMOS (HVNMOS). A P-well and an N-well are respectively formed on a P type dopant epitaxial silicon layer formed on a wafer or substrate. The N-well region plays the role of drain in the structure. Field oxide regions
2
are formed on the N-well to reduce the electric field near the drain. A gate oxide
4
is formed on the surface of the both wells and adjacent to the field oxide
2
. A gate
6
, typically composed of polysilicon, is formed on the gate oxide. A drain contact
8
is formed in the N-well by doping impurities into a desired region of the well. In general, the dopant concentration of the drain contact
8
is higher than that of the N-well. The source
10
is formed in the P-well adjacent to the gate, typically the source
10
is created by conventional ion implantation. An isolation layer
12
is deposited on the gate
6
and a portion of the dual well to expose a portion of the source
10
and the drain
8
. The channel region of the HVNMOS is located within the P-well under the gate oxide
4
.
The MOS is a four-terminal device, a contact can also be made to the body region. A bias can also be applied between the source and body and such a bias will have an impact on threshold voltage (Vt). The impact of the source-body bias on Vt is referred to the body effect. Unfortunately, in the structure of the aforesaid HVNMOS, the P-well is directly short circuit to the P-substrate. Thus, the aforementioned HVNMOS suffers the issue of the body effect arisen by the P-substrate short to the source. Further, the device can not allow negative voltage operation.
What is needed in the art is a method to form a HVMOS in an epitaxial layer and semiconductor substrate which has a high breakdown voltage and to eliminate the body effect induced by the P-substrate.
SUMMARY
An object of the present invention is to provide a structure of a HVNMOS and the method of the same.
Another object of the present invention is to form a HVNMOS with an N
+
buried layer combined with N-well to solate the P-well, thereby eliminating the body effect.
A further object of the present invention is to provide a HVNMOS that can be operated in negative voltage operation.
In accordance with the present invention, a HVNMOS is provided. The device includes a N
+
buried layer in a substrate. A P-well is formed with P type dopant in an epitaxial layer on the buried layer. N-wells surround the P-well and the N-wells are also formed in the epitaxial layer. The P-well is isolated by the N-well adjacent to the P-well and the N
+
buried layer. One of the N-well regions acts the drain in the structure. A plurality of field oxide regions is formed on the N-well or P-well to define the active area of the device. A gate oxide is formed on the surface of the P-well and the N-well served as the drain. A gate is formed on the gate oxide. A drain contact is formed in the N-well for drain by doping impurities into a desired region of the well. In a preferred embodiment, the concentration of the dopant is higher than that of the N-well for drain. The source region of the device is referred to a bulk pick-up source, which is consisted of a P type doped region adjacent to a N type doped region. Both of the P and N type doped region are formed in the P-well adjacent to the drain. An isolation layer is deposited on the gate and a portion of the P-well and N-well for drain. The channel region of the HVNMOS is located within the P-well under the gate oxide.
The method according to the present invention includes providing a single crystal P substrate with an N
+
buried layer formed therein. P epitaxial layer is then formed on the surface of the P substrate. The N-well and P-well are respectively formed in the epitaxial layer by ion implantation and thermally diffusion. The P-well is isolated by the N-wells and the N
+
buried layer. A plurality of isolation structure such as field oxide (FOX) regions are created for the purposes of defining the active area. Typically, the FOX regions are created via a conventional method.
Subsequently, a thin oxide layer is formed on the epitaxial layer to act as a gate dielectric. A doped polysilicon layers is deposited by chemical vapor deposition on the gate oxide layer. Then, the doped polysilicon layer and the gate dielectric layer are patterned to form gate structures on the P-well and N-well. An N
+
drain contact in the drain (N-well) and a source region in the P-well over the N
+
buried layer are formed by conventional manner. The source region of the device is consisted of a P type doped region and an N type doped region. The P type doped region is adjacent to the N type doped region. An isolation layer is patterned on the gate structure for isolation.


REFERENCES:
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patent: 4862242 (1989-08-01), Wildi
patent: 5017996 (1991-05-01), Yasuoka
patent: 5070381 (1991-12-01), Scott
patent: 5087954 (1992-02-01), Shirai
patent: 5105252 (1992-04-01), Kim
patent: 5227654 (1993-07-01), Momose
patent: 5242854 (1993-09-01), Solheim
patent: 5311054 (1994-05-01), DeJong
patent: 2193036-A (1988-01-01), None

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