Method of forming a gate stack containing a gate dielectric...

Details Method of forming a gate stack containing a gate dielectric... Method of forming a gate stack containing a gate dielectric...

2005-09-30

2008-12-30

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21190

Reexamination Certificate

active

07470591

ABSTRACT:
A method is provided for reducing the metal content and controlling the metal depth profile of a gate dielectric layer in a gate stack. The method includes providing a substrate in a process chamber, depositing a gate dielectric layer on the substrate, where the gate dielectric layer includes a metal element. The metal element is selectively etched from at least a portion of the gate dielectric layer to form an etched gate dielectric layer with reduced metal content, and a gate electrode layer is formed on the etched gate dielectric layer.

REFERENCES:
patent: 6891231 (2005-05-01), Bojarczuk, Jr. et al.
patent: 2004/0206724 (2004-10-01), Nallan et al.
patent: 2006/0060565 (2006-03-01), Nallan et al.

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