Method of forming a dual damascene structure on a semiconductor

Details Method of forming a dual damascene structure on a semiconductor Method of forming a dual damascene structure on a semiconductor

1999-10-08

2000-08-15

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438622, 438624, 438634, 438700, 438735, 438737, 438738, 438739, 438740, 438749, H01L 214763, H01L 21311, H01L 21302, H01L 21461

Patent

active

061036196

ABSTRACT:
The present invention provides a method of forming a dual damascene structure on a semiconductor wafer. The semiconductor wafer comprises a substrate, and a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer and a photoresist layer sequentially formed on the substrate. A dry-etching process is performed first to vertically remove a specific portion of the second silicon oxide layer down to the silicon nitride layer so as to form a hole. Then the photoresist layer is removed and the portion of the silicon nitride layer positioned under the hole is removed using a phosphoric acid solution. A lithographic process is then performed to form a photoresist layer on the second silicon oxide layer, the photoresist layer comprising a line-shaped opening positioned above the hole with a width larger than the diameter of the hole. Then an etching process is performed along the line-shaped opening to vertically remove the second silicon oxide layer and the first silicon oxide layer. The photoresist layer is then removed completely. Finally, a metallic layer is deposited and a CMP process is performed to form a conductive wire coupled with the via plug on the semiconductor wafer.

REFERENCES:
patent: 5635423 (1997-06-01), Huang et al.
patent: 5880004 (1999-03-01), Ho

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