Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-08-16
2005-08-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S691000
Reexamination Certificate
active
06930040
ABSTRACT:
In a method of the present invention, an intermediate structure having a top surface is provided. An isolation trench is formed is the intermediate structure. Isolation material is deposited over the intermediate structure. The isolation material fills the isolation trench. Excess isolation material extends above the top surface of the intermediate structure. Part of the excess isolation material is removed until there is a predetermined thickness of isolation material remaining on the top surface of the intermediate structure. A contact opening is formed in the isolation material at the isolation trench. The contact opening extends through at least part of the intermediate structure. Contact material is deposited over the isolation material. The contact material fills the contact opening. Excess contact material, if any, that extends above the isolation material is removed. The excess isolation material is removed at least until the top surface of the intermediate structure is reached.
REFERENCES:
patent: 6096594 (2000-08-01), Lin et al.
patent: 6184584 (2001-02-01), Sakao
patent: 6194739 (2001-02-01), Ivanov et al.
patent: 6221775 (2001-04-01), Ference et al.
patent: 6350661 (2002-02-01), Lim et al.
Hu, C., “SOI and Nanoscale MOSFETs,” Plenary Paper, Dept. of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA.
Yang, F.L., et al., “25 nm CMOS Omega FETs,” IEEE 2002.
Colinge, J.P., et al., “SOI Devices of Sub-0.1 βm Gate Lengths,” Proc. 23rdInternational Conference on Microelectronics (MIEL 2002), vol. 1, NIS, Yugoslavia, May 12-15, 2002, pp. 109-113.
Chen Ying-Ho
Hou Chuan-Ping
Jang Syun-Ming
Tseng Tung-Ching
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
LandOfFree
Method of forming a contact on a silicon-on-insulator wafer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a contact on a silicon-on-insulator wafer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a contact on a silicon-on-insulator wafer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3517556