Method of forming a contact hole in a semiconductor...

Details Method of forming a contact hole in a semiconductor... Method of forming a contact hole in a semiconductor...

1999-06-18

2001-04-24

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S624000, C438S639000

Reexamination Certificate

active

06221714

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 98-25172, filed on Jun. 29, 1998, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a contact hole fabrication, and more particularly to a method of forming a contact hole using oxide spacers on sidewalls of a contact hole to protect gate protecting spacers.
BACKGROUND OF THE INVENTION
One important technique for fabricating a semiconductor device involves forming a connection between an upper level wiring layer and either a conductive region of an impurity-diffused layer in a semiconductor substrate or a lower level wiring layer. Such a connection is preferably formed through a contact hole formed in an interlayer insulating film.
Recently as the density of integrated circuits has increased, the design rule, i.e., the minimum feature size, has decreased. As a result, the distance between gate stacks in a semiconductor device is being shortened to coordinate this reduced design rule. Accordingly, a contact hole opened in the interlayer insulating layer between the gate stacks has a high aspect ratio and an over-etch is implemented during a step of etching the interlayer insulating layer. However, such an over-etch may also etch a silicon nitride gate spacer that operates to protect the gate stacks.
FIGS. 1A
to
1
D are cross-sectional views at selected stages of a conventional fabrication process for forming a contact hole between gate stacks.
FIG. 1A
schematically shows a semiconductor substrate
10
having a cell array region and a core region, each area having a plurality of gate stacks
18
. Each gate stack
18
includes a gate oxide layer
11
, a gate electrode
15
, and a silicon nitride capping layer
16
. The gate electrode
15
is generally made of a multilayer structure of a polysilicon layer
12
and a tungsten silicide layer
14
. A first silicon nitride layer
20
is generally deposited over the entire surface of the semiconductor substrate
10
and the plurality of gate stacks
18
by a conventional method such as chemical vapor deposition (CVD).
The first silicon nitride layer
20
is then etched back to form spacers
21
on both sidewalls of the gate stacks
18
as shown in
FIG. 1B. A
second silicon nitride layer
22
is then deposited over the resulting structure, including the substrate
10
and the gate stacks
18
, to serve as an etching stopper. An interlayer insulating layer
24
is then deposited over the gate stacks
18
and in the spaces between the gate stacks
18
.
Referring to
FIG. 1C
, selected portions of the interlayer insulating layer
24
are etched to form a plurality of contact holes
26
between the gate stacks
18
using the second silicon nitride layer
22
as an etching stopper.
After forming the contact holes
26
, the second silicon nitride layer
22
between the gate stacks is removed as shown in FIG.
1
D.
The above-mentioned method uses silicon nitride for the capping layer
16
, the gate spacer
21
, and the etching stopper
22
. As a result, the gate spacer
21
and the capping layer
16
are also etched during the step of etching the second silicon nitride layer
22
, as shown in inside the dotted circle of FIG.
1
D. Accordingly, the gate electrode
15
may electrically contact the subsequently-formed conductive bit line and storage node pads (or landing pads).
SUMMARY OF THE INVENTION
The present invention was made in view of the above problem, and it is therefore an object of the invention to provide a method of forming a contact hole between the gate stacks without etching the gate spacer and gate capping layer. A key feature of this invention is to form a protective spacer layer having an etching selectivity with respect to the silicon nitride layer after forming the contact hole. The protective layer is preferably formed on the sidewalls of the contact hole with a silicon oxide layer. The protective silicon oxide layer acts to protect an underlying silicon nitride layer. The silicon oxide layer forms a gate stack spacer together with the underlying silicon nitride layer on sidewalls of the gate stacks. The present invention provides double gate spacers comprised of two different layers having an etching selectivity with respect to each other.
In accordance with these and other objects, a method of forming a contact hole in a semiconductor device is provided, including forming at least two gate stacks over a semiconductor substrate, forming a first insulating layer over the semiconductor substrate and at least two gate stacks, forming an interlayer insulating layer over the first insulating layer, etching a selected portion of the interlayer insulating layer to form a contact hole between the gate stacks, forming a second insulating layer over the interlayer insulating layer, the contact hole and the semiconductor substrate, etching back the second insulating layer to form spacers on sidewalls of the contact hole, and using the interlayer insulating layer and the spacers as a mask to etch the first insulating layer to expose a top surface of the semiconductor substrate.
In this method, the first insulating layer preferably comprises silicon nitride and has a thickness of about 50 Å to 100 Å. The first insulating layer preferably serves as an etching stopper during the etching of the interlayer insulating layer. The second insulating layer comprises silicon oxide and has a thickness of about 300 Å to 500 Å.
Each of the gate stacks preferably comprises a gate oxide layer, a gate electrode, and a gate capping insulating layer. The gate capping insulating layer preferably comprises silicon nitride.
A method of forming a contact hole in a semiconductor substrate is also provided in which the semiconductor substrate has a cell array region and a core region, the cell array region having at least two first gate stacks and the core region having at least two second gate stacks. This method includes forming first and second insulating layers over the semiconductor substrate, the first gate stacks, and the second gate stacks, forming a first photoresist layer over the second insulating layer to cover the cell array region and to expose the core region, using the first photoresist layer as a mask to etch the first and second insulating layers to form first spacers on sidewalls of the second gate stacks, removing the first photoresist layer, forming a second photoresist layer to cover the core region and to expose the cell array region, using the second photoresist layer as a mask to etch the second insulating layer to expose the first insulating layer, removing the second photoresist layer, forming an interlayer insulating layer over the semiconductor substrate, the first gate stacks, and the second gate stacks, etching a selected portion of the interlayer insulating layer to form a contact hole between the first gate stacks, forming a third insulating layer over the semiconductor substrate, the first gate stacks, the second gate stacks, and the contact hole, etching the third insulating layer to form second spacers on sidewalls of the contact hole, and using the interlayer insulating layer and the second spacers as a mask to etch the first insulating layer to expose a top surface of the semiconductor substrate.
In this method, the first insulating layer preferably comprises silicon nitride and has a thickness of about 50 Å to 100
521
. The first insulating layer preferably serves as an etching stopper during the etching of the interlayer insulating layer. The second insulating layer preferably comprises silicon oxide and has a thickness of about 500 Å. The third insulating layer preferably comprises silicon oxide and has a thickness of about 300 Å to 500 Å.
Each of the gate stacks preferably comprises a gate oxide layer, a gate electrode, and a gate capping insulating layer. The gate capping insulating layer preferably comprises silicon nitride.


REFERENCES:
patent: 5786249 (1998-07-01), Denninson
patent: 5933755 (1999-08-01)

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