Method of forming a cob dram by using self-aligned node and bit

Details Method of forming a cob dram by using self-aligned node and bit Method of forming a cob dram by using self-aligned node and bit

1998-07-08

2000-11-21

Elms, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438265, 437257, 257400, H01L 218242

Patent

active

061502138

ABSTRACT:
The present invention includes forming polysilicon plugs between the gate structures and word lines in a BPSG layer formed on the gate structures and the word lines. A polysilicon layer, a tungsten silicide layer and a silicon oxide layer are sequentially formed on the BPSG layer. Then, the multi-layers are etched to the surface of the BPSG layer. Next, the BPSG layer is slightly etched to expose the polysilicon plug. Oxide spacers are formed on the sidewalls of the layers. A silicon nitride layer is formed over the bit lines, oxide spacers and on the polysilicon plugs. An oxide layer is formed on the silicon nitride layer. Subsequently, the oxide layer is patterned to form node contact holes. An etching is used to etch the silicon nitride layer. A first conductive layer is formed along the surface of the oxide layer, the contact holes. The top portion of the first conductive layer is removed. The oxide layer is removed to expose the silicon nitride layer. A dielectric film is deposited along the surface of the first conductive layer. Finally, a second conductive layer is formed over the dielectric film.

REFERENCES:
patent: 5126280 (1992-06-01), Cha et al.
patent: 5150276 (1992-09-01), Gonzalez et al.
patent: 5229314 (1993-07-01), Okudaira et al.

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