Method of forming a CMOS transistor having ultra shallow...

Details Method of forming a CMOS transistor having ultra shallow... Method of forming a CMOS transistor having ultra shallow...

1999-05-11

2003-02-18

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S303000, C438S514000, C438S528000, C438S557000, C438S487000

Reexamination Certificate

active

06521501

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to transistor and more specifically to a method of forming transistors with ultra shallow source and drain regions.
BACKGROUND
Ultra large scale integration (ULSI) requires that complementary metal oxide semiconductors (CMOS) devices have very small device geometries. Thus, the capability of forming ultra shallow source/drain regions in CMOS devices is critical. At these very small geometries, careful attention must be paid to thermal cycles to which the CMOS device is subjected.
A conventional process for forming a CMOS device is described with respect to
FIGS. 1A-1D
. An oxide layer is formed over a conventional substrate layer
102
(e.g., a silicon wafer) by, for example, oxidizing the surface of the substrate layer
102
. Next, a polycrystalline silicon (“polysilicon”) layer is formed over the oxide layer by, e.g., a conventional chemical vapor deposition (CVD) technique. Portions of the polysilicon and oxide layers are removed by, e.g., a conventional etch technique, to produce oxide layer
104
and gate structure
106
.
FIG. 1A
depicts the resulting structure
100
A.
Next, dopants are implanted into the structure
100
A using a conventional technique to form shallow source/drain areas
108
. The resulting structure is shown in FIG.
1
B.
Next, insulative sidewall spacers are
110
formed by forming an insulator layer over structure
100
B and then removing portions of the insulator layer. The resulting structure is shown in FIG.
1
C.
Next, dopants are implanted into the structure
100
C to form conventional source/drain areas
112
. The resulting structure
100
D is shown in FIG.
1
D.
Next, to activate the dopants implanted in shallow source/drain areas
108
and source/drain areas
112
, the structure
100
D is heated using, e.g., a rapid thermal annealing (RTA) to a temperature of 400 to 500° C. for approximately 10 seconds.
Next, a silicide layer such as titanium (Ti) or Cobalt (Co) is formed over structure
100
D. The resulting structure is next heated to a temperature of approximately 400 to 700° C. to react the silicide layer with exposed portions of the silicon substrate layer
102
(hereafter “silicidation reaction”).
Providing energy, such as heat, deactivates some dopants in the shallow source/drain areas
108
and source/drain areas
112
. However, common dopants such as arsenic (As) are known to deactivate at temperatures as low as 400° C. Dopant deactivation may not be a concern for dopant species with high solid solubilities in silicon and/or in lightly doped drain (LDD) regions. However, careful attention must be paid to heating for larger dopant atoms such as antimony (Sb) or indium (In) and/or where required doping levels are above the equilibrium solubility of silicon. The silicidation reaction occurring between about 400 to 700° C. may be sufficient to cause significant loss of available charge carriers in the shallow source/drain areas
108
and source/drain areas
112
.
A further side effect of heating is the diffusion of active carriers from the shallow source/drain areas
108
and source/drain areas
112
. The diffusion effectively increases the depth of the source/drain areas, possibly beyond acceptable design depths. The diffusion is a particular problem when ultra shallow source/drain regions are desired.
Thus, what is needed is a method to form CMOS devices having ultra shallow source/drain regions with acceptable carrier concentrations and shallow depth.
SUMMARY
One embodiment of the present invention includes a method of forming a CMOS structure, the method including the acts of: forming a gate structure over a substrate layer; forming a silicide layer over the substrate layer; forming shallow source/drain areas in the substrate layer; forming an oxide diffusion barrier layer over the structure; forming a metal absorption layer over the oxide diffusion barrier layer; and melting portions of the substrate layer directly overlying the shallow source/drain areas, thereby transforming the shallow source/drain areas into shallow source/drain regions. In one embodiment, the act of melting includes exposing the metal absorption layer to pulsed laser beams.
Various embodiments of the present invention will be more fully understood in light of the following detailed description taken together with the accompanying drawings.


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patent: 5474940 (1995-12-01), Tsukamoto
patent: 5536684 (1996-07-01), Dass et al.
patent: 5633522 (1997-05-01), Dorleans et al.
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patent: 6184097 (2001-02-01), Yu
Talwar, et al., “Ultra-Shallow, Abrupt, and Highly-Activated Junctions by Low-Energy Ion Implantation and Laser Annealing”, IEEE, Ion Implantation Technology Proceedings, pp. 1171-1174, Jun. 1998.

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