Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-01-30
2007-01-30
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S051000, C438S055000, C438S064000, C438S106000, C438S112000, C438S124000, C438S126000, C438S127000, C438S460000, C257S668000
Reexamination Certificate
active
10767952
ABSTRACT:
A method of fabricating a chip-scale or wafer-level package having passivation layers on substantially all surfaces thereof to form a hermetically sealed package. The package may be formed by disposing a first passivation layer on the passive or backside surface of a semiconductor wafer. The semiconductor wafer may be attached to a flexible membrane and diced, such as by a wafer saw, to separate the semiconductor devices. Once diced, the flexible membrane may be stretched so as to laterally displace the individual semiconductor devices away from one another and substantially expose the side edges thereof. Once the side edges of the semiconductor devices are exposed, a passivation layer may be formed on the side edges and active surfaces of the devices. A portion of the passivation layer over the active surface of each semiconductor device may be removed so as to expose conductive elements formed therebeneath.
REFERENCES:
patent: 3924323 (1975-12-01), Trevail et al.
patent: 5136364 (1992-08-01), Byrne
patent: 5389182 (1995-02-01), Mignardi
patent: 5451550 (1995-09-01), Wills et al.
patent: 5682065 (1997-10-01), Farnworth et al.
patent: 5742094 (1998-04-01), Ting
patent: 5851911 (1998-12-01), Farnworth
patent: 5933713 (1999-08-01), Farnworth
patent: 5956605 (1999-09-01), Akram et al.
patent: 6008070 (1999-12-01), Farnworth
patent: 6063646 (2000-05-01), Okuno et al.
patent: 6074896 (2000-06-01), Dando
patent: 6251703 (2001-06-01), Van Campenhout et al.
patent: 6303977 (2001-10-01), Schroen et al.
patent: 6387185 (2002-05-01), Doering et al.
patent: 6399464 (2002-06-01), Muntifering et al.
patent: 6656820 (2003-12-01), Liu
patent: 6909784 (2005-06-01), Sugahara
patent: 6964915 (2005-11-01), Farnworth et al.
patent: 2001/0018229 (2001-08-01), Kato et al.
patent: 2002/0192927 (2002-12-01), Yamada
patent: 2003/0071354 (2003-04-01), Tsai et al.
patent: 2004/0023438 (2004-02-01), Egawa et al.
patent: 2004/0121514 (2004-06-01), Yoo et al.
patent: 2005/0073058 (2005-04-01), Kuo et al.
patent: 2005/0085008 (2005-04-01), Derderian et al.
patent: 2005/0104221 (2005-05-01), Memis
patent: 2006/0005911 (2006-01-01), Kubo et al.
Jr. Carl Whitehead
Mitchell James M.
TraskBritt
LandOfFree
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