Method of fabricating variable length vertical transistors

Details Method of fabricating variable length vertical transistors Method of fabricating variable length vertical transistors

2002-10-03

2003-10-14

Chen, Jack (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S269000, C438S138000, C257S328000

Reexamination Certificate

active

06632712

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods!used to fabricate semiconductor devices, and more specifically to a method used to fabricate vertical transistors featuring variable channel lengths.
(2) Description of Prior Art
The advent of micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron, or deep sub-micron features, has allowed a greater number of smaller semiconductor chips to be obtained from a specific size starting semiconductor substrate, resulting in a reduction of processing costs for a specific semiconductor chip. The smaller semiconductor chips still offer device densities equal to, or greater than, counterpart semiconductor chips, comprised with larger features. Advances in specific semiconductor disciplines, such as photolithography, have allowed the attainment of sub-micron features to be routinely achieved. The use of more sophisticated exposure cameras, as well as the development of more sensitive photoresist materials, have allowed images of less than 0.25 um to be resolved for photoresist shapes and for features defined using these deep sub-micron photoresist shapes as an etch mask. Still the limiting resolution provided by present photolithographic procedures, restrict the level of miniaturization available for horizontal type, semiconductor devices.
This invention will describe the fabrication of vertical type semiconductor devices, in which the channel length of a metal oxide semiconductor field effect (MOSFET) device is not defined by limiting photolithographic procedures, but by the thickness of deposited materials. This invention will also describe a unique fabrication process for vertical type, complimentary metal oxide semiconductor (CMOS), featuring both P channel (PMOS), and N channel (NMOS), devices, with the ability to form variable length channel lengths. Prior art, such as Hause et al, in U.S. Pat. No. 6,069,384, describe a method of fabricating a vertical transistor structure, however that prior art does not offer the process described in this present invention in which both NMOS and PMOS vertical devices are formed with variable channel lengths.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate vertical, metal oxide semiconductor field effect transistors (MOSFET), devices, on a semiconductor substrate.
It is another object of this invention to form vertical devices featuring variable channel lengths, specific channel lengths for specific devices, with the vertical channel length determined by the thickness of a deposited insulator, or deposited composite insulator layer.
It is still another object of this invention to form CMOS devices, P channel (PMOS), and N channel (NMOS), devices, comprised with variable channel length devices, on the same semiconductor chip.
In accordance with the present invention a method of fabricating vertical CMOS devices on a semiconductor chip, featuring devices comprised with variable channel lengths, is described. A heavily doped N type region, to be used as a drain region for a subsequent vertical NMOS device, is formed in a first region of a semiconductor substrate, followed by formation of a heavily doped P type region, to be used as a drain region for a subsequent vertical PMOS device, in a second region of the semiconductor substrate. After deposition of a first silicon oxide layer and of a first silicon nitride layer, patterning procedures are employed to remove the first silicon nitride layer from the first silicon oxide layer in the PMOS region. Deposition of a second silicon nitride layer and of an overlying second silicon oxide layer results in a first composite insulator layer in the NMOS region comprised of second silicon oxide layer, second silicon nitride layer, first silicon nitride layer, and first silicon oxide layer, while a thinner, second composite insulator layer, comprised of second silicon oxide layer, second silicon nitride layer, and first silicon oxide layer resides in the PMOS region. Channel openings are next formed in the first composite insulator layer exposing a portion of the top surface of the N type drain region, and in the thinner, second composite insulator layer exposing a portion of the top surface of the P type drain region. An epitaxial silicon layer is then selectively grown filling the channel openings. A thin polysilicon layer is then deposited followed by photolithographic masking procedures allowing the portion of the thin polysilicon layer located in the NMOS region to be doped N type via ion implantation procedures, then allowing the portion of thin polysilicon layer, located in the PMOS region, to be doped P type. After deposition of a third silicon oxide layer photolithographic and selective dry etch procedures are used to remove exposed portions of third silicon oxide layer, of N type and P type, thin polysilicon layer, and of second silicon oxide layer, with the selective dry etch procedure terminating at the appearance of the second silicon nitride layer, creating thin polysilicon shapes, to be used as source regions, and creating underlying second silicon oxide shapes to be used as insulator spacers for the subsequent CMOS devices. After removal of the photoresist mask used for definition of the above shapes a wet etch procedure is employed to remove second and first silicon nitride layers in the NMOS region, exposing a first length of selective epitaxial silicon to be used for the NMOS channel region, and to remove second silicon nitride layer in the PMOS region, exposing a shorter length of selective epitaxial silicon to be used for the PMOS channel region. A silicon dioxide gate insulator layer is formed on the channel regions, as well as on the sides of the N type, and P type polysilicon shapes. A thick polysilicon layer is deposited and again doped N type in the NMOS region, and doped P type in the PMOS region. A selective, anisotropic dry etch procedure removes regions of thick polysilicon layer not covered by the overlying third silicon oxide—thin polysilicon—second silicon oxide shapes, resulting in: a vertical NMOS device, comprised of a thick, N type polysilicon shape, surrounding the silicon dioxide gate insulator layer in a region in which the gate insulator layer overlays a channel region comprised of the first length of selective epitaxial silicon; and a vertical PMOS device, comprised of a thick, P type polysilicon shape, surrounding the silicon dioxide gate insulator layer in a region in which the gate insulator layer overlays a channel region comprised of a shorter, second length of selective epitaxial silicon. Each channel region is located between an overlying thin, doped polysilicon source and silicon oxide spacers, and underlying heavily doped drain regions.


REFERENCES:
patent: 5918115 (1999-06-01), Kikuchi et al.
patent: 5963800 (1999-10-01), Augusto
patent: 6069384 (2000-05-01), Hause et al.
patent: 6084264 (2000-07-01), Darwish
patent: 6225165 (2001-05-01), Noble, Jr. et al.
patent: 6461900 (2002-10-01), Sundaresan et al.

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