Method of fabricating semiconductor device by exposing upper...

Details Method of fabricating semiconductor device by exposing upper... Method of fabricating semiconductor device by exposing upper...

2006-10-05

2009-10-20

Andújar, Leonardo (Department: 2893)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S629000, C438S672000, C438S673000

Reexamination Certificate

active

07605035

ABSTRACT:
According to some embodiments, a method includes forming at least two contact plugs that penetrate an insulating layer to connect with a semiconductor substrate. The contact plugs have an upper surface and upper sidewalls that are higher than a top surface of the insulating layer. An etch stop covers the contact plugs and the insulating layer, and a molding layer is formed over the etch stop layer. The molding layer is etched to form a molding pattern having an opening. A bottom of the opening includes a central region that exposes the etch stop on the upper surface and a peripheral region that extends from the central region and the etch stop layer. The etch stop is etched to expose the upper surface. Storage electrodes are formed to contact the contact plugs. The molding pattern is removed to expose the storage electrodes. Other embodiments are described and claimed.

REFERENCES:
patent: 5597756 (1997-01-01), Fazan et al.
patent: 6168989 (2001-01-01), Chiang et al.
patent: 6531372 (2003-03-01), Lee et al.
patent: 6548853 (2003-04-01), Hwang et al.
patent: 6569689 (2003-05-01), Marsh
patent: 2003-0057598 (2003-07-01), None
English language abstract of Korean Publication No. 2003-0057598.

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