Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-03
2001-09-11
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S981000
Reexamination Certificate
active
06287912
ABSTRACT:
The present invention relates to techniques for fabricating semiconductor devices and, more particularly, to techniques applicable to the fabrication of a semiconductor device provided with gate insulating films of differing thickness formed on a semiconductor substrate.
A voltage of an external power supply at a level specified by an I/O (input-output) standard is applied to MISFETs (metal-insulator semiconductor field-effect transistors) included in an I/O circuit or the like among the transistors included in a semiconductor device, and a different voltage must be applied to MISFETs included in internal circuits of the semiconductor device for the optimum functioning of those MISFETs. For example, it is advantageous to apply a voltage higher than that applied to peripheral circuits to a MIS transistor included in a memory cell of a DRAM (dynamic random-access memory) which is capable of retaining information therein to extend the data retaining time. However, in a microcomputer logic LSI circuit, a voltage lower than a supply voltage must be applied to a MIS transistor included in the internal circuit to enable high-speed operations and to reduce power consumption.
The field strength exerted on a gate insulating film must be kept at a predetermined value to prevent the breakdown of the gate of a MISFET. Therefore, when only one gate insulating film is formed on a semiconductor substrate, the gate insulating film is formed with a thickness meeting the requirement of a high-voltage part. However, when the gate insulating film is formed with such a thickness, the field strength in a low-voltage part decreases and hence the driving ability of the MISFET decreases. Consequently, the signal processing speed of the LSI circuit including the MISFET is reduced. To prevent the reduction of the signal processing speed of the LSI circuit, a part of the gate insulating film corresponding to the high-voltage part needs to be formed with a relatively great thickness, and a part of the gate insulating film corresponding to the low-voltage part needs to be formed with a relatively small thickness; that is, two gate insulating films having respectively different design thicknesses are formed on the semiconductor substrate. A semiconductor device having a microprocessor is mentioned in, for example, U.S. Pat. No. 5,057,448.
SUMMARY OF THE INVENTION
The inventors of the present invention have studied a doping technique for adjusting the threshold voltages of an n-channel MISFET and a p-channel MISFET in a semiconductor device provided with the n-channel MISFET and the p-channel MISFET formed on a semiconductor substrate and provided with at least two gate insulating films having respectively different thicknesses. This doping technique uses separate photoresist masks for the ion implantation of a dopant to adjust the threshold voltages of the n-channel MISFET and the p-channel MISFET. The inventors of the present invention have found the following problems in this doping technique which uses separate photoresist masks for the ion implantation of dopants to adjust the threshold voltages of the n-channel MISFET and the p-channel MISFET.
This known technique needs an increased number of photomasks and an increased number of processes for forming photoresist patterns and for removing the photoresist patterns, which inevitably leade to an increase in the time required for fabricating semiconductor devices, as well as semiconductor device manufacturing costs. Furthermore, since processes for forming and removing photoresist patterns produce foreign matter, an increase in the number of processes reduces the reliability and the yield rate of the semiconductor devices.
The inventors of the present invention have made investigations into known threshold voltage adjusting techniques for adjusting the threshold voltages of MISFETs included in semiconductor devices and provided with a plurality of gate insulating films respectively having different thicknesses. A method relating to a technique of this kind is disclosed in Japanese Patent Laid-Open No. Hei 1-114069. According to this technique, a method of fabricating a semiconductor device, provided with a low-voltage MIS transistor formed on a substrate, and a high-voltage MIS transistor formed on the same substrate, uses a photoresist film for removing a part of an insulating film corresponding to a region for the gate of the low-pressure MIS transistor for introducing an impurity by ion implantation into a region for a channel to change the impurity concentration of the channel before removing the photoresist film. However nothing is disclosed in Japanese Patent Laid-Open No. Hei 1-114069 about a technique for adjusting the threshold voltage when forming an n-channel MISFET and a p-channel MISFET on a substrate or a technique for adjusting the threshold voltage of the high-voltage MIS transistor.
Accordingly, it is an object of the present invention to provide a technique which is capable of adjusting the threshold voltages of a p-channel FET (field-effect transistor) having a relatively thin gate insulating film and an n-channel FET without increasing the number of photomasks and the number of processes for forming and removing photoresist patterns.
Another object of the present invention is to provide a technique which is capable of easily adjusting the threshold voltages of an n-channel FET and a p-channel FET included in a semiconductor device having a substrate provided with two gate insulating films respectively having different thicknesses.
According to a first aspect of the present invention, a method of fabricating a semiconductor device having a semiconductor substrate provided thereon with a relatively thick gate insulating film and a relatively thin gate insulating film comprises the steps of:
(a) forming a first insulating film in regions in a surface of the semiconductor substrate in which the relatively thick gate insulating film and the relatively thin gate insulating film are to be formed;
(b) forming a mask exposing a region in which the relatively thin gate insulating film is to be formed, and covering other regions following the step (a);
(c) introducing an impurity for adjusting the threshold voltages of n-channel FETs and p-channel FETs having the relatively thin gate insulating film into the exposed regions not covered with the mask;
(d) etching parts of the first insulating film, not covered with the mask by using the mask as an etching mask following the step (c); and
(e) forming the relatively thick gate insulating film and the relatively thin gate insulating film on the semiconductor substrate following the step (d).
According to a second aspect of the present invention, a method of fabricating a semiconductor device having a semiconductor substrate provided thereon with a relatively thick gate insulating film and a relatively thin gate insulating film comprises the steps of:
(a) forming a first mask having a pattern exposing first regions and covering other regions on the semiconductor substrate, and introducing an impurity for adjusting the threshold voltage of n-channel FETs having the relatively thick gate insulating film in the exposed first regions of the semiconductor substrate;
(b) forming a second mask having a pattern exposing second regions and covering other regions on the semiconductor substrate, and introducing an impurity for adjusting the threshold voltage of p-channel FETs having the relatively thick gate insulating film into the exposed second regions of the semiconductor substrate;
(c) forming a first insulating film in regions in which the relatively thick gate insulating film and the relatively thin gate insulating film are to be formed on the semiconductor substrate following the steps (a) and (b);
(d) forming a third mask having a pattern exposing a region in which the relatively thin gate insulating film is to be formed, and covering other regions following the step (c);
(e) introducing an impurity for adjusting the threshold voltages of the n-channel FETs and the p-channel FETs having the relatively th
Asakura Hisao
Miyamoto Masafumi
Nagai Ryo
Nakamura Masayuki
Sekiguchi Toshihiro
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Nelms David
Vu David
LandOfFree
Method of fabricating semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2497581