Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-24
2002-04-09
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S399000, C438S650000, C438S688000
Reexamination Certificate
active
06368910
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an improved memory device and method of fabricating the same. More specifically, the present invention relates to a method for improving the contact mechanism between the storage node and the device area of memory devices such as dynamic random access memory (DRAM) and ferroelectric random access memory (FRAM), as well as the improved memory cells so fabricated. The method disclosed in the present invention eliminates the need for an additional barrier layer, which is typically required in order to prevent the deterioration of the contact structure between the conventional metal plug and the poly-silicon (poly-Si) plug, or between the conventional metal plug and the silicon (Si) devices.
BACKGROUND OF THE INVENTION
A semiconductor memory cell, such as dynamic random access memory (DRAM) or ferroelectric random access memory (FRAM), contains a storage node(including an electrode of a capacitor), which is in contact with the device area. Providing an appropriate contact mechanism between the capacitor storage node and the device area is a critical consideration in the integration of ferroelectric or high dielectric constant perovskite (CaTiO
3
) films into the semiconductor memory devices.
Typically, the electrode materials for use in preparing the capacitor storage node require the presence of certain barriers which can block the diffusion of the perovskite elements and/or elements from the Si-devices and prevent interactions between these components. Several prior art references have discussed the difficulties during the process of integrating of a BST capacitor, which contains (Ba, Sr)TiO
3
, due to the fact that all the electrode materials (such as Pt, Ru, Ir, and conducting oxides thereof) require a certain barrier layer at their interface with the Si-plug, which connects the capacitor with the cell transistor. Binary or ternary refractory metal nitrides (such as TiN, TiSiN, TiAlN, etc), are used to protect the storage electrode from reacting with Si atoms during the steps of BST film deposition, high temperature annealing, and insulating layer deposition. This has been discussed in, for example, U.S. Pat. No. 5,998,225.
The conventional stack of barrier/electrode is prone to oxidation during the BST deposition because of the exposure of the sidewall area to the oxidizing atmosphere. When the barrier layer is buried in the contact plug, the sidewall of the barrier is not exposed to the oxidizing atmosphere, and the oxidation resistant property of the contact is improved. However, the buried barrier scheme has at least one shortcoming in that, if there is any displacement between the contact plug and the electrode, the barrier layer can still suffer from oxidation. Furthermore, with devices features at 0.13 &mgr;m and below, it becomes increasingly difficult to implement such a barrier layer, and there is no room for misalignment between the contact hole and the electrode.
The oxidation resistance of TiN or TiAlN is another concern when using either of these materials as the barrier layer between an SrRuO
3
electrode and a contact plug (either a metal plug or a poly-Si plug). It has been reported that TiAlN film exhibits a better oxidation resistance than the TiN film, and that the amount of aluminum (about 9%) included in the TiN film plays an important role in increasing the oxidation resistance by forming an Al
2
O
3
layer at the top surface. However, the thickness of the Al-rich (Al
2
O
3
) layer usually needs to be greater than 20 nm. This can cause a capacitance of the integrated BST capacitor to be substantially reduced.
SUMMARY OF THE INVENTION
The primary object of the present invention is to develop an improved contact between the storage node of a memory cell with an associated device area without the need for a barrier layer. More specifically, the primary object of the present invention is to develop a method which provides an improved contact between a capacitor electrode and a semiconductor device (with or without a poly-Si plug), without the need for a barrier, which is required to protect the storage electrode from reacting with Si atoms during the fabrication process. As discussed above, the use of such a barrier layer can cause many undesirable problems such as oxidation, misalignment between the contact hole and the electrode, and degradation in the capacitance of the storage mode.
In the present invention, a Ru metal film or conductive RuO
2
/Ru stacked film is used to form a plug, which provides the contact between the electrode of the capacitor and the poly-Si plug, or between the electrode of the capacitor and the semiconductor device area if no intermediate poly-Si plug is used. The implementation of such Ruthenium-based contact plug can prevent the deterioration of the metal plug (bottom electrode) caused by the underneath poly-Si plug or the Si device (if no such immediate poly-Si plug is present), thus it allows the memory device to be fabricated without the need for a barrier layer. As a result, the process of the present invention allows a better alignment between the contact hole and the electrode. Also, unlike the case of using an TiAlN barrier, the method of the present invention does not involve an insulative Al
2
O
3
layer, thus, no degradation of the total capacitance of the integrated ferroelectric or high dielectric constant capacitor will be incurred.
REFERENCES:
patent: 5998225 (1999-12-01), Crenshaw et al.
patent: 6156599 (2000-05-01), Aoyama et al.
Chiang Ming-Chung
Chu Chung-Ming
Liu Wen-Chung
Sheu Bor-Bu
Sun Pai-Hsuan
Huynh Yennhu B.
Liauh W. Wayne
Nguyen Tuan H.
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