Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-09-09
2000-03-21
Nelms, David
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438282, 438283, H01L 21336
Patent
active
060402199
ABSTRACT:
A method for manufacturing a power semiconductor device including a semi-insulating polycrystalline silicon (SIPOS) film is provided. According to this method, first, a conductive collector region is formed in a semiconductor substrate. Then, a first insulating film, which exposes a portion of the semiconductor substrate in which a base region is to be formed, is formed on said semiconductor substrate in which the collector region is formed. A conductive base region is formed in the collector region. A second insulating film is formed over the entire surface of the semiconductor substrate. After exposing a portion of the semiconductor substrate in which an emitter region and a channel stop region are to be formed, impurities for the emitter region are implanted into the base region. Simultaneously, a third insulating film is formed over the entire surface of the semiconductor substrate, while a conductive emitter region is formed by diffusing the impurities. At least one of the first to third insulating films is left only in a field region between the base region and the channel stop region. Parts of the base region, the emitter region, and the channel stop region are exposed after forming a semi-insulating polycrystalline silicon (SIPOS) film on the entire surface of the resultant structure. A base electrode, an emitter electrode, and an equipotential metal ring are then formed, respectively contacting the base region, the emitter region, and the channel stop region.
REFERENCES:
patent: 4454526 (1984-06-01), Nishizawa
patent: 4733287 (1988-03-01), Bower
patent: 4800415 (1989-01-01), Simmons et al.
patent: 4803176 (1989-02-01), Bower
patent: 5060047 (1991-10-01), Jaume et al.
patent: 5410177 (1995-04-01), Harmel et al.
patent: 5424563 (1995-06-01), Temple et al.
patent: 5608237 (1997-03-01), Aizawa et al.
patent: 5773868 (1998-06-01), Endo
patent: 5923071 (1999-07-01), Saito
Takeshi Matsushita et al., "Highly Reliable High-Voltage Transistors by Use of the SIPOS Process", IEEE Transactions on Electron Devices, vol. ED-23, No. 8, Aug. 1976.
A. Mimura et al., "High-Voltage Planar Structure Using SiO2-SIPOS-SiO2 Film", IEEE Electron Device Letters, vol. EDL-6, No. 4, Apr. 1985.
D. Jaume et al., "High-Voltage Planar Devices Using Field Plate and Semi-Resistive Layers", IEEE Transactions on Electron Devices, vol. 38, No. 7, Jul. 1991.
Park Chan-ho
Park Jae-Hong
Lebentritt Michael S.
Nelms David
Samsung Electronics Co,. Ltd.
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