Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-04-26
2011-04-26
Vu, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257SE21423
Reexamination Certificate
active
07932154
ABSTRACT:
In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.
REFERENCES:
patent: 4101921 (1978-07-01), Shimada et al.
patent: 5241499 (1993-08-01), Camerlenghi
patent: 5812449 (1998-09-01), Song
patent: 6388293 (2002-05-01), Ogura et al.
patent: 6815764 (2004-11-01), Bae et al.
patent: 6867453 (2005-03-01), Shin et al.
patent: 6958272 (2005-10-01), Lingunis et al.
patent: 7042045 (2006-05-01), Kang et al.
patent: 7045848 (2006-05-01), Shukuri
patent: 2002/0074590 (2002-06-01), Jong et al.
patent: 2001-168219 (2001-06-01), None
patent: 10-0142602 (1998-04-01), None
patent: 10-0187656 (1999-01-01), None
patent: 2000-0027286 (2000-05-01), None
Chen, Chun, et al., “Analysis of Enhanced Hot-Carrier Effects in Scaled Flash Memory Devices”, IEEE Transactions on Electron Devices, vol. 45, No. 7, pp. 1524-1530, (Jul. 1998).
Cho In-Wook
Kang Sung-Taeg
Kim Sang-Su
Yang Jeong-hwan
Lee & Morse P.C.
Samsung Electronics Co,. Ltd.
Vu David
Ziskind David
LandOfFree
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