Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-05-13
2004-06-22
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S286000, C438S305000
Reexamination Certificate
active
06753227
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims benefit of priority from Korean Patent Application No. 2002-48042, filed on Aug. 14, 2002, the contents of which are hereby incorporated by reference in their entirety for all purposes.
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The disclosure relates to methods of fabricating a semiconductor device and, more specifically, to methods of fabricating a MOS transistor.
2. Description of the Related Art
As semiconductor devices become more highly integrated, a giga-bit scale Dynamic Random Access Memory (DRAM) has been recently introduced. In the gigabit scale DRAM, a minimum design rule is reduced to 0.1 &mgr;m or less. This results in the following problems that degrade operation characteristics of the semiconductor devices during a fabrication process.
To highly integrate a semiconductor device, local oxidation of silicon (LOCOS) processes tend to be replaced by shallow trench isolation (STI) processes for forming a field oxide region. However, the STI process causes much more stress of the semiconductor substrate than the LOCOS process, and thus the semiconductor substrate often has damages such as extended defects. [IBM J. RES. DEVELOP. v.36, p.170, 1992]
In addition, as semiconductor devices are highly integrated, the channel length of a MOS transistor becomes shorter. Thus, short channel effects may occur and threshold voltages may decrease. In order to compensate for the decreasing threshold voltage, an impurity doping concentration of a channel region should be increased. An ion implantation process is widely used for forming source/drain regions of a MOS transistor. In the ion implantation process, if impurity doses exceed a critical value, combinations among silicon atoms may be broken, so that impurity-doped regions may be changed into an amorphous state. However, the broken combination of silicon atoms may be cured in a successive thermal process, so that the impurity-doped regions regain a crystalline structure containing impurities. In this case, atomic defects gather locally to form an electrically stable structure. Thus, discontinuous regions between the stable structures may be present, forming extended defects such as a dislocation or a stacking fault. [“Formation of extended defects in silicon by high energy implantation of B and P”, J. Y. Cheng et. al., J. Appl. Phys., v.80 (4), p.2105, 1996], [“Annealing behaviors of dislocation loops near projected range in high-dose as implanted (001) Si”, S. N. Hsu, et. al., J. Appl. Phys. v. 86 (9), p.4503, 1990]
These extended defects may disturb a normal operation of a semiconductor device.
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IBM J. Res. Develop. V.36, p. 170, 1992.
Formation of extended defects in silicon by high energy implantation of B and P, J.Y. Cheng, et al., J. Appl. Phys., v.80 (4), p. 2105, 1996.
Annealing behaviors of dislocation loops near projected range in high-does as implanted (001) Si, S.N. Hsu, et al., J. Appl. Phys. V. 86 (9), p. 4503, 1990.
Cho Chang-Hyun
Kim Ki-Nam
Koh Gwan-Hyeob
Lindsay Jr. Walter L.
Marger & Johnson & McCollom, P.C.
Niebling John F.
Samsung Electronics Co,. Ltd.
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